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Carla Shamee Mckinney

Examiner (ID: 15579)

Most Active Art Unit
2898
Art Unit(s)
2898
Total Applications
14
Issued Applications
0
Pending Applications
14
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15200529 [patent_doc_number] => 10497768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Organic light-emitting display apparatus and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/013899 [patent_app_country] => US [patent_app_date] => 2016-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8890 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15013899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/013899
Organic light-emitting display apparatus and method of manufacturing the same Feb 1, 2016 Issued
Array ( [id] => 11063962 [patent_doc_number] => 20160260924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURNG THE SAME' [patent_app_type] => utility [patent_app_number] => 15/002139 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5425 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002139
ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURNG THE SAME Jan 19, 2016 Abandoned
Array ( [id] => 10780196 [patent_doc_number] => 20160126352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/994549 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8950 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994549 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994549
HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR Jan 12, 2016 Abandoned
Array ( [id] => 10802781 [patent_doc_number] => 20160148938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A GATE AND A CONDUCTIVE LINE IN A PILLAR PATTERN' [patent_app_type] => utility [patent_app_number] => 14/992866 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4537 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992866 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992866
SEMICONDUCTOR DEVICE HAVING A GATE AND A CONDUCTIVE LINE IN A PILLAR PATTERN Jan 10, 2016 Abandoned
Array ( [id] => 10740690 [patent_doc_number] => 20160086842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Method for Producing a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 14/955592 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5136 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955592 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/955592
Method for Producing a Semiconductor Device Nov 30, 2015 Abandoned
Array ( [id] => 11425073 [patent_doc_number] => 20170033219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION' [patent_app_type] => utility [patent_app_number] => 14/949977 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3410 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949977
Semiconductor device including fin having condensed channel region Nov 23, 2015 Issued
Array ( [id] => 13769469 [patent_doc_number] => 10177084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Semiconductor module and method of manufacturing semiconductor module [patent_app_type] => utility [patent_app_number] => 15/534686 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7268 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15534686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/534686
Semiconductor module and method of manufacturing semiconductor module Nov 5, 2015 Issued
Array ( [id] => 10689504 [patent_doc_number] => 20160035650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY' [patent_app_type] => utility [patent_app_number] => 14/884076 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14884076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/884076
Non-bridging contact via structures in proximity Oct 14, 2015 Issued
Array ( [id] => 10826212 [patent_doc_number] => 20160172380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MODIFIED FIN CUT AFTER EPITAXIAL GROWTH' [patent_app_type] => utility [patent_app_number] => 14/836264 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836264
MODIFIED FIN CUT AFTER EPITAXIAL GROWTH Aug 25, 2015 Abandoned
Array ( [id] => 11439312 [patent_doc_number] => 20170040333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'Contact Plug Constrained By Dielectric Portions' [patent_app_type] => utility [patent_app_number] => 14/817093 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7032 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/817093
Contact Plug Constrained By Dielectric Portions Aug 2, 2015 Abandoned
Array ( [id] => 11339515 [patent_doc_number] => 20160365271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/813775 [patent_app_country] => US [patent_app_date] => 2015-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7778 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/813775
Fin field effect transistor (FinFET) device structure with interconnect structure Jul 29, 2015 Issued
Array ( [id] => 11425038 [patent_doc_number] => 20170033184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION' [patent_app_type] => utility [patent_app_number] => 14/809688 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809688 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809688
SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION Jul 26, 2015 Abandoned
Array ( [id] => 10448244 [patent_doc_number] => 20150333258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'Non-volatile memory device comprising a ferroelectric film and a paraelectric film.' [patent_app_type] => utility [patent_app_number] => 14/808494 [patent_app_country] => US [patent_app_date] => 2015-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5437 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14808494 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/808494
Non-volatile memory device comprising a ferroelectric film and a paraelectric film. Jul 23, 2015 Abandoned
Array ( [id] => 10448082 [patent_doc_number] => 20150333096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'LAMINATED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/807488 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14807488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/807488
Laminated semiconductor device Jul 22, 2015 Issued
Array ( [id] => 11398120 [patent_doc_number] => 20170018657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'VERTICAL JFET MADE USING A REDUCED MASK SET' [patent_app_type] => utility [patent_app_number] => 14/798631 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798631 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798631
VERTICAL JFET MADE USING A REDUCED MASK SET Jul 13, 2015 Abandoned
Array ( [id] => 10433215 [patent_doc_number] => 20150318228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'MODULE AND METHOD FOR PRODUCING MODULE' [patent_app_type] => utility [patent_app_number] => 14/797752 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7729 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14797752 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/797752
MODULE AND METHOD FOR PRODUCING MODULE Jul 12, 2015 Abandoned
Array ( [id] => 10426294 [patent_doc_number] => 20150311305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SPIN MOSFET' [patent_app_type] => utility [patent_app_number] => 14/793173 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793173
SPIN MOSFET Jul 6, 2015 Abandoned
Array ( [id] => 11840093 [patent_doc_number] => 20170221814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/329464 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13463 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15329464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/329464
Semiconductor device Jun 30, 2015 Issued
Array ( [id] => 10590763 [patent_doc_number] => 09312386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Method for forming fin FET structure with dual-stress spacers' [patent_app_type] => utility [patent_app_number] => 14/752940 [patent_app_country] => US [patent_app_date] => 2015-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 4839 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752940 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752940
Method for forming fin FET structure with dual-stress spacers Jun 27, 2015 Issued
Array ( [id] => 16067751 [patent_doc_number] => 10692839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => GaN devices on engineered silicon substrates [patent_app_type] => utility [patent_app_number] => 15/574822 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7847 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/574822
GaN devices on engineered silicon substrates Jun 25, 2015 Issued
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