Carla Shamee Mckinney
Examiner (ID: 15579)
Most Active Art Unit | 2898 |
Art Unit(s) | 2898 |
Total Applications | 14 |
Issued Applications | 0 |
Pending Applications | 14 |
Abandoned Applications | 0 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 18440235
[patent_doc_number] => 20230187530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/547072
[patent_app_country] => US
[patent_app_date] => 2021-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10590
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547072
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/547072 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | Dec 8, 2021 | Pending |
Array
(
[id] => 17477747
[patent_doc_number] => 20220085251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => LIGHT EMITTING DIODE HAVING SIDE REFLECTION LAYER
[patent_app_type] => utility
[patent_app_number] => 17/537341
[patent_app_country] => US
[patent_app_date] => 2021-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13919
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537341
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/537341 | Light emitting diode having side reflection layer | Nov 28, 2021 | Issued |
Array
(
[id] => 18394799
[patent_doc_number] => 20230163020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => BURIED POWER RAIL AFTER REPLACEMENT METAL GATE
[patent_app_type] => utility
[patent_app_number] => 17/531837
[patent_app_country] => US
[patent_app_date] => 2021-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7221
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531837
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/531837 | BURIED POWER RAIL AFTER REPLACEMENT METAL GATE | Nov 21, 2021 | Pending |
Array
(
[id] => 18176990
[patent_doc_number] => 20230037719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => METHODS OF FORMING BOTTOM DIELECTRIC ISOLATION LAYERS
[patent_app_type] => utility
[patent_app_number] => 17/531726
[patent_app_country] => US
[patent_app_date] => 2021-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4876
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531726
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/531726 | METHODS OF FORMING BOTTOM DIELECTRIC ISOLATION LAYERS | Nov 19, 2021 | Pending |
Array
(
[id] => 17780123
[patent_doc_number] => 20220246473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => HYBRID FILM SCHEME FOR SELF-ALIGNED CONTACT
[patent_app_type] => utility
[patent_app_number] => 17/524830
[patent_app_country] => US
[patent_app_date] => 2021-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524830
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/524830 | HYBRID FILM SCHEME FOR SELF-ALIGNED CONTACT | Nov 11, 2021 | Pending |
Array
(
[id] => 17431823
[patent_doc_number] => 20220059532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/521011
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10862
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521011
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/521011 | Method of manufacturing a semiconductor device | Nov 7, 2021 | Issued |
Array
(
[id] => 17692167
[patent_doc_number] => 20220199460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/520967
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7800
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520967
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520967 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE | Nov 7, 2021 | Pending |
Array
(
[id] => 18891115
[patent_doc_number] => 11869893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Stacked field effect transistor with wrap-around contacts
[patent_app_type] => utility
[patent_app_number] => 17/511647
[patent_app_country] => US
[patent_app_date] => 2021-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10354
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511647
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/511647 | Stacked field effect transistor with wrap-around contacts | Oct 26, 2021 | Issued |
Array
(
[id] => 17886631
[patent_doc_number] => 20220302109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/502554
[patent_app_country] => US
[patent_app_date] => 2021-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12856
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502554
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/502554 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Oct 14, 2021 | Pending |
Array
(
[id] => 18284171
[patent_doc_number] => 20230099643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => NANOSHEET TRANSISTORS WITH SELF-ALIGNED GATE CUT
[patent_app_type] => utility
[patent_app_number] => 17/490266
[patent_app_country] => US
[patent_app_date] => 2021-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6649
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490266
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/490266 | NANOSHEET TRANSISTORS WITH SELF-ALIGNED GATE CUT | Sep 29, 2021 | Pending |
Array
(
[id] => 18768477
[patent_doc_number] => 11818901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-14
[patent_title] => Integrated circuit including bipolar transistors
[patent_app_type] => utility
[patent_app_number] => 17/489425
[patent_app_country] => US
[patent_app_date] => 2021-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3881
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489425
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/489425 | Integrated circuit including bipolar transistors | Sep 28, 2021 | Issued |
Array
(
[id] => 17347350
[patent_doc_number] => 20220013681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => GERMANIUM PHOTODIODE
[patent_app_type] => utility
[patent_app_number] => 17/486219
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3374
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486219
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/486219 | Germanium photodiode | Sep 26, 2021 | Issued |
Array
(
[id] => 18269104
[patent_doc_number] => 20230090346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => Stacked FET with Independent Gate Control
[patent_app_type] => utility
[patent_app_number] => 17/482928
[patent_app_country] => US
[patent_app_date] => 2021-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8295
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482928
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/482928 | Stacked FET with Independent Gate Control | Sep 22, 2021 | Pending |
Array
(
[id] => 19444645
[patent_doc_number] => 12094937
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-17
[patent_title] => Stacked field effect transistor devices with replacement gate
[patent_app_type] => utility
[patent_app_number] => 17/481537
[patent_app_country] => US
[patent_app_date] => 2021-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 30
[patent_no_of_words] => 8517
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481537
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/481537 | Stacked field effect transistor devices with replacement gate | Sep 21, 2021 | Issued |
Array
(
[id] => 18266824
[patent_doc_number] => 20230088066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH ENHANCED ON-RESISTANCE AND BREAKDOWN VOLTAGE
[patent_app_type] => utility
[patent_app_number] => 17/481204
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14059
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481204
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/481204 | FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH ENHANCED ON-RESISTANCE AND BREAKDOWN VOLTAGE | Sep 20, 2021 | Pending |
Array
(
[id] => 18841493
[patent_doc_number] => 11849590
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Capacitor comprising a bismuth metal oxide-based lead titanate thin film
[patent_app_type] => utility
[patent_app_number] => 17/479542
[patent_app_country] => US
[patent_app_date] => 2021-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3637
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479542
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/479542 | Capacitor comprising a bismuth metal oxide-based lead titanate thin film | Sep 19, 2021 | Issued |
Array
(
[id] => 17933533
[patent_doc_number] => 20220328659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/475068
[patent_app_country] => US
[patent_app_date] => 2021-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13479
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475068
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/475068 | Semiconductor device and manufacturing method thereof | Sep 13, 2021 | Issued |
Array
(
[id] => 18223385
[patent_doc_number] => 20230062379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => Semiconductor Strutures With Dielectric Fins
[patent_app_type] => utility
[patent_app_number] => 17/460757
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460757
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460757 | Semiconductor Strutures With Dielectric Fins | Aug 29, 2021 | Pending |
Array
(
[id] => 18228593
[patent_doc_number] => 20230067587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/460200
[patent_app_country] => US
[patent_app_date] => 2021-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6521
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460200
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460200 | Semiconductor devices and methods of manufacturing thereof | Aug 27, 2021 | Issued |
Array
(
[id] => 18228431
[patent_doc_number] => 20230067425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/460203
[patent_app_country] => US
[patent_app_date] => 2021-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9210
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460203
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460203 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF | Aug 27, 2021 | Pending |