Carla Shamee Mckinney

Array ( [id] => 9350276 [patent_doc_number] => 08669167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-11 [patent_title] => 'Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices' [patent_app_type] => utility [patent_app_number] => 13/596687 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5060 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13596687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9355198 [patent_doc_number] => 08673731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices' [patent_app_type] => utility [patent_app_number] => 13/589707 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4031 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9515394 [patent_doc_number] => 20140151886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/233388 [patent_app_country] => US [patent_app_date] => 2012-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4260 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14233388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9266601 [patent_doc_number] => 20140021517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'Semiconductor Device and Fabrication Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/551107 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4284 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9831793 [patent_doc_number] => 08940606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Method for fabricating trench type power transistor device' [patent_app_type] => utility [patent_app_number] => 13/543877 [patent_app_country] => US [patent_app_date] => 2012-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4115 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13543877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9831813 [patent_doc_number] => 08940626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Integrated circuit and method for fabricating the same having a replacement gate structure' [patent_app_type] => utility [patent_app_number] => 13/541979 [patent_app_country] => US [patent_app_date] => 2012-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 595 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13541979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8615336 [patent_doc_number] => 20130020647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/540799 [patent_app_country] => US [patent_app_date] => 2012-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 88 [patent_figures_cnt] => 88 [patent_no_of_words] => 35535 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13540799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9202369 [patent_doc_number] => 20140001546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/538577 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12197 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9202341 [patent_doc_number] => 20140001518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'Integrated Circuit Devices with Well Regions and Methods for Forming the Same' [patent_app_type] => utility [patent_app_number] => 13/539027 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 3769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10544682 [patent_doc_number] => 09269819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Semiconductor device having a gate and a conductive line in a pillar pattern' [patent_app_type] => utility [patent_app_number] => 13/538877 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4489 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9202344 [patent_doc_number] => 20140001520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'CONTACT RESISTANCE REDUCED P-MOS TRANSISTORS EMPLOYING GE-RICH CONTACT LAYER' [patent_app_type] => utility [patent_app_number] => 13/539200 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9412 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9178441 [patent_doc_number] => 20130320427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'GATED CIRCUIT STRUCTURE WITH SELF-ALIGNED TUNNELING REGION' [patent_app_type] => utility [patent_app_number] => 13/487627 [patent_app_country] => US [patent_app_date] => 2012-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9178437 [patent_doc_number] => 20130320422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM' [patent_app_type] => utility [patent_app_number] => 13/484657 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 8408 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12478359 [patent_doc_number] => 09991375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Metal gate electrode of a semiconductor device [patent_app_type] => utility [patent_app_number] => 13/484047 [patent_app_country] => US [patent_app_date] => 2012-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8441966 [patent_doc_number] => 20120258582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'METHOD AND APPARATUS FOR SELECTIVELY GROWING DOPED EPITAXIAL FILM' [patent_app_type] => utility [patent_app_number] => 13/478854 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10384 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9402273 [patent_doc_number] => 08692327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Lateral double diffused metal oxide semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/476207 [patent_app_country] => US [patent_app_date] => 2012-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3977 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13476207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9158767 [patent_doc_number] => 20130307044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'Selective Air Gap Isolation In Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 13/472337 [patent_app_country] => US [patent_app_date] => 2012-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10834 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13472337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10652468 [patent_doc_number] => 09368738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Thin film transistor and method of manufacturing the same, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/472247 [patent_app_country] => US [patent_app_date] => 2012-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 9539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13472247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12040508 [patent_doc_number] => 09818742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Semiconductor device isolation using an aligned diffusion and polysilicon field plate' [patent_app_type] => utility [patent_app_number] => 13/469917 [patent_app_country] => US [patent_app_date] => 2012-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1560 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13469917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9704526 [patent_doc_number] => 08829594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Nonvolatile programmable switches' [patent_app_type] => utility [patent_app_number] => 13/469867 [patent_app_country] => US [patent_app_date] => 2012-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 15982 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13469867 [rel_patent_id] =>[rel_patent_doc_number] =>)