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Carla Shamee Mckinney

Examiner (ID: 15579)

Most Active Art Unit
2898
Art Unit(s)
2898
Total Applications
14
Issued Applications
0
Pending Applications
14
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18670143 [patent_doc_number] => 11777055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Light emitting device [patent_app_type] => utility [patent_app_number] => 17/349183 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/349183
Light emitting device Jun 15, 2021 Issued
Array ( [id] => 17130330 [patent_doc_number] => 20210305099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Integrated Circuit Devices with Well Regions and Methods for Forming the Same [patent_app_type] => utility [patent_app_number] => 17/345659 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345659
Integrated circuit devices with well regions and methods for forming the same Jun 10, 2021 Issued
Array ( [id] => 19341441 [patent_doc_number] => 12051638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Integrated high efficiency transistor cooling [patent_app_type] => utility [patent_app_number] => 17/344231 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3593 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344231
Integrated high efficiency transistor cooling Jun 9, 2021 Issued
Array ( [id] => 17115873 [patent_doc_number] => 20210296470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR DEVICE LAYOUT STRUCTURE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/303879 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303879
Semiconductor device layout structure manufacturing method Jun 8, 2021 Issued
Array ( [id] => 19093904 [patent_doc_number] => 11955369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Recessed local interconnect formed over self-aligned double diffusion break [patent_app_type] => utility [patent_app_number] => 17/341640 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 3963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341640 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341640
Recessed local interconnect formed over self-aligned double diffusion break Jun 7, 2021 Issued
Array ( [id] => 19168564 [patent_doc_number] => 11984478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Forming source and drain features in semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/341745 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 58 [patent_no_of_words] => 11977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341745
Forming source and drain features in semiconductor devices Jun 7, 2021 Issued
Array ( [id] => 17115853 [patent_doc_number] => 20210296450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/340802 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340802
Semiconductor device and methods of manufacture Jun 6, 2021 Issued
Array ( [id] => 17949565 [patent_doc_number] => 20220336584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => NANOSHEET FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING [patent_app_type] => utility [patent_app_number] => 17/341034 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341034
Nanosheet field-effect transistor device and method of forming Jun 6, 2021 Issued
Array ( [id] => 18721586 [patent_doc_number] => 11798943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Transistor source/drain contacts and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/339452 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 11465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339452
Transistor source/drain contacts and methods of forming the same Jun 3, 2021 Issued
Array ( [id] => 19328974 [patent_doc_number] => 12046666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Gallium nitride (GaN) based transistor with multiple p-GaN blocks [patent_app_type] => utility [patent_app_number] => 17/330012 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7281 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330012
Gallium nitride (GaN) based transistor with multiple p-GaN blocks May 24, 2021 Issued
Array ( [id] => 19277450 [patent_doc_number] => 12027583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Gate structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/320170 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 7371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320170
Gate structures for semiconductor devices May 12, 2021 Issued
Array ( [id] => 19277244 [patent_doc_number] => 12027376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Method for cut metal gate etch dimensional control [patent_app_type] => utility [patent_app_number] => 17/313535 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 15513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313535
Method for cut metal gate etch dimensional control May 5, 2021 Issued
Array ( [id] => 17010929 [patent_doc_number] => 20210242090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => Etch Stop Layer Between Substrate and Isolation Structure [patent_app_type] => utility [patent_app_number] => 17/240007 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240007
Etch stop layer between substrate and isolation structure Apr 25, 2021 Issued
Array ( [id] => 17963915 [patent_doc_number] => 20220344496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => Method and Structure for Reducing Source/Drain Contact Resistance at Wafer Backside [patent_app_type] => utility [patent_app_number] => 17/236675 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236675
Method and structure for reducing source/drain contact resistance at wafer backside Apr 20, 2021 Issued
Array ( [id] => 17040627 [patent_doc_number] => 20210257263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => NMOS and PMOS Transistor Gates with Hafnium Oxide Layers and Lanthanum Oxide Layers [patent_app_type] => utility [patent_app_number] => 17/232381 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232381
NMOS and PMOS Transistor Gates with Hafnium Oxide Layers and Lanthanum Oxide Layers Apr 15, 2021 Pending
Array ( [id] => 18782333 [patent_doc_number] => 11824100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Gate structure of semiconductor device and method of forming same [patent_app_type] => utility [patent_app_number] => 17/232282 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232282
Gate structure of semiconductor device and method of forming same Apr 15, 2021 Issued
Array ( [id] => 18690020 [patent_doc_number] => 11785781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Integrated circuit constructions comprising memory and methods used in the formation of integrated circuitry comprising memory [patent_app_type] => utility [patent_app_number] => 17/226524 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5736 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17226524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/226524
Integrated circuit constructions comprising memory and methods used in the formation of integrated circuitry comprising memory Apr 8, 2021 Issued
Array ( [id] => 18804467 [patent_doc_number] => 11837631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Source/drain spacer with air gap in semiconductor devices and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/226896 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 96 [patent_no_of_words] => 9747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17226896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/226896
Source/drain spacer with air gap in semiconductor devices and methods of fabricating the same Apr 8, 2021 Issued
Array ( [id] => 17933531 [patent_doc_number] => 20220328657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/225786 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225786
Integrated circuit structure and manufacturing method thereof Apr 7, 2021 Issued
Array ( [id] => 18766934 [patent_doc_number] => 11817343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Dielectric gap fill [patent_app_type] => utility [patent_app_number] => 17/222012 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 7704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222012
Dielectric gap fill Apr 4, 2021 Issued
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