Search

Carlos Lugo

Examiner (ID: 6896, Phone: (571)272-7058 , Office: P/3675 )

Most Active Art Unit
3675
Art Unit(s)
3676, 3675, 3674, 3677, 3627, 3673
Total Applications
2136
Issued Applications
1455
Pending Applications
153
Abandoned Applications
552

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19544985 [patent_doc_number] => 20240362021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INSTRUCTIONS FOR REMOTE ATOMIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/670427 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670427
INSTRUCTIONS FOR REMOTE ATOMIC OPERATIONS May 20, 2024 Pending
Array ( [id] => 19603177 [patent_doc_number] => 20240394057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => RISC-V VECTOR EXTENTION CORE, PROCESSOR, AND SYSTEM ON CHIP [patent_app_type] => utility [patent_app_number] => 18/667528 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667528
RISC-V VECTOR EXTENTION CORE, PROCESSOR, AND SYSTEM ON CHIP May 16, 2024 Pending
Array ( [id] => 19320177 [patent_doc_number] => 20240241721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => RE-USING PROCESSING ELEMENTS OF AN ARTIFICIAL INTELLIGENCE PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/622727 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622727
RE-USING PROCESSING ELEMENTS OF AN ARTIFICIAL INTELLIGENCE PROCESSOR Mar 28, 2024 Pending
Array ( [id] => 19219867 [patent_doc_number] => 20240184571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Accelerated Vector Reduction Operations [patent_app_type] => utility [patent_app_number] => 18/524391 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524391 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524391
Accelerated Vector Reduction Operations Nov 29, 2023 Pending
Array ( [id] => 19660534 [patent_doc_number] => 20240427599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 18/339529 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339529
PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-BASED DEVICES Jun 21, 2023 Pending
Array ( [id] => 18694769 [patent_doc_number] => 20230325186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => PROCESSING-IN-MEMORY (PIM) SYSTEM AND OPERATING METHODS OF THE PIM SYSTEM [patent_app_type] => utility [patent_app_number] => 18/334659 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334659
PROCESSING-IN-MEMORY (PIM) SYSTEM AND OPERATING METHODS OF THE PIM SYSTEM Jun 13, 2023 Pending
Array ( [id] => 18651537 [patent_doc_number] => 20230297373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE [patent_app_type] => utility [patent_app_number] => 18/307088 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307088
INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE Apr 25, 2023 Pending
Array ( [id] => 19250997 [patent_doc_number] => 20240201987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => NEURAL NETWORK HARDWARE ACCELERATION VIA SEQUENTIALLY CONNECTED COMPUTATION MODULES [patent_app_type] => utility [patent_app_number] => 18/067015 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067015
NEURAL NETWORK HARDWARE ACCELERATION VIA SEQUENTIALLY CONNECTED COMPUTATION MODULES Dec 15, 2022 Pending
Array ( [id] => 19251008 [patent_doc_number] => 20240201998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => PERFORMING STORAGE-FREE INSTRUCTION CACHE HIT PREDICTION IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/083185 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083185
PERFORMING STORAGE-FREE INSTRUCTION CACHE HIT PREDICTION IN A PROCESSOR Dec 15, 2022 Pending
Array ( [id] => 18297304 [patent_doc_number] => 20230106990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => EXECUTING MULTIPLE PROGRAMS SIMULTANEOUSLY ON A PROCESSOR CORE [patent_app_type] => utility [patent_app_number] => 18/078422 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078422
Executing multiple programs simultaneously on a processor core Dec 8, 2022 Issued
Array ( [id] => 18271026 [patent_doc_number] => 20230092268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => BRANCH TYPE LOGGING IN LAST BRANCH REGISTERS [patent_app_type] => utility [patent_app_number] => 17/992407 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992407
BRANCH TYPE LOGGING IN LAST BRANCH REGISTERS Nov 21, 2022 Pending
Array ( [id] => 18223651 [patent_doc_number] => 20230062645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PARALLEL INSTRUCTION EXTRACTION METHOD AND READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/981336 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981336
PARALLEL INSTRUCTION EXTRACTION METHOD AND READABLE STORAGE MEDIUM Nov 3, 2022 Abandoned
Array ( [id] => 19084728 [patent_doc_number] => 20240111529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => VECTOR PROCESSING UNIT WITH PROGRAMMABLE MULTICYCLE SHUFFLE UNIT [patent_app_type] => utility [patent_app_number] => 17/957672 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957672
VECTOR PROCESSING UNIT WITH PROGRAMMABLE MULTICYCLE SHUFFLE UNIT Sep 29, 2022 Pending
Array ( [id] => 18864176 [patent_doc_number] => 20230418612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => AUTOMATIC FUSION OF ARITHMETIC IN-FLIGHT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/848284 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848284
AUTOMATIC FUSION OF ARITHMETIC IN-FLIGHT INSTRUCTIONS Jun 22, 2022 Pending
Array ( [id] => 17869446 [patent_doc_number] => 20220292183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SECURE CONTROL FLOW PREDICTION [patent_app_type] => utility [patent_app_number] => 17/826622 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826622
SECURE CONTROL FLOW PREDICTION May 26, 2022 Pending
Array ( [id] => 20494262 [patent_doc_number] => 12536132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Data processing engine tile architecture for an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/826070 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826070
Data processing engine tile architecture for an integrated circuit May 25, 2022 Issued
Array ( [id] => 17809410 [patent_doc_number] => 20220261245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => PREDICATION METHODS FOR VECTOR PROCESSORS [patent_app_type] => utility [patent_app_number] => 17/738993 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738993
PREDICATION METHODS FOR VECTOR PROCESSORS May 5, 2022 Pending
Array ( [id] => 17659358 [patent_doc_number] => 20220179823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => RECONFIGURABLE REDUCED INSTRUCTION SET COMPUTER PROCESSOR ARCHITECTURE WITH FRACTURED CORES [patent_app_type] => utility [patent_app_number] => 17/681163 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/681163
RECONFIGURABLE REDUCED INSTRUCTION SET COMPUTER PROCESSOR ARCHITECTURE WITH FRACTURED CORES Feb 24, 2022 Pending
Array ( [id] => 17659192 [patent_doc_number] => 20220179657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => APPARATUS, SYSTEMS, AND METHODS FOR LOW POWER COMPUTATIONAL IMAGING [patent_app_type] => utility [patent_app_number] => 17/525398 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525398
Apparatus, systems, and methods for low power computational imaging Nov 11, 2021 Issued
Array ( [id] => 17629439 [patent_doc_number] => 20220164454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => HARDWARE MODULE AND ITS CONTROL METHOD WITH A 32-BIT INSTRUCTION EXTENSION FOR PROCESSOR SUPPORTING ARIA ENCRYPTION AND DECRYPTION [patent_app_type] => utility [patent_app_number] => 17/510884 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510884
Hardware module and its control method with a 32-bit instruction extension for processor supporting ARIA encryption and decryption Oct 25, 2021 Issued
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