Search

Carlos Lugo

Examiner (ID: 6896, Phone: (571)272-7058 , Office: P/3675 )

Most Active Art Unit
3675
Art Unit(s)
3676, 3675, 3674, 3677, 3627, 3673
Total Applications
2136
Issued Applications
1455
Pending Applications
153
Abandoned Applications
552

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7653124 [patent_doc_number] => 20110302393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'CONTROL SYSTEMS AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/153724 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8565 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302393.pdf [firstpage_image] =>[orig_patent_app_number] => 13153724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153724
CONTROL SYSTEMS AND DATA PROCESSING METHOD Jun 5, 2011 Abandoned
Array ( [id] => 9096414 [patent_doc_number] => 20130275725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'INTEGRATED CIRCUIT DEVICE AND METHOD FOR PERFORMING CONDITIONAL NEGATION OF DATA' [patent_app_type] => utility [patent_app_number] => 13/995190 [patent_app_country] => US [patent_app_date] => 2011-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995190 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995190
INTEGRATED CIRCUIT DEVICE AND METHOD FOR PERFORMING CONDITIONAL NEGATION OF DATA Jan 2, 2011 Abandoned
Array ( [id] => 8255188 [patent_doc_number] => 20120159513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'MESSAGE PASSING IN A CLUSTER-ON-CHIP COMPUTING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 12/968880 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20120159513.pdf [firstpage_image] =>[orig_patent_app_number] => 12968880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/968880
Message passing in a cluster-on-chip computing environment Dec 14, 2010 Issued
Array ( [id] => 8176138 [patent_doc_number] => 20120110037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Methods and Apparatus for a Read, Merge and Write Register File' [patent_app_type] => utility [patent_app_number] => 12/916931 [patent_app_country] => US [patent_app_date] => 2010-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5161 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110037.pdf [firstpage_image] =>[orig_patent_app_number] => 12916931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916931
Methods and Apparatus for a Read, Merge and Write Register File Oct 31, 2010 Abandoned
Array ( [id] => 5948542 [patent_doc_number] => 20110107059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'MULTILAYER PARALLEL PROCESSING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/916833 [patent_app_country] => US [patent_app_date] => 2010-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107059.pdf [firstpage_image] =>[orig_patent_app_number] => 12916833 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916833
MULTILAYER PARALLEL PROCESSING APPARATUS AND METHOD Oct 31, 2010 Abandoned
Array ( [id] => 5948555 [patent_doc_number] => 20110107064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'DATA PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/915158 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13179 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107064.pdf [firstpage_image] =>[orig_patent_app_number] => 12915158 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/915158
Semiconductor device with instruction code and prefix code predecoders Oct 28, 2010 Issued
Array ( [id] => 8176591 [patent_doc_number] => 20120110309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Data Output Transfer To Memory' [patent_app_type] => utility [patent_app_number] => 12/916163 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110309.pdf [firstpage_image] =>[orig_patent_app_number] => 12916163 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916163
Data Output Transfer To Memory Oct 28, 2010 Abandoned
Array ( [id] => 7588576 [patent_doc_number] => 20110283087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'IMAGE FORMING APPARATUS, IMAGE FORMING METHOD, AND COMPUTER READABLE MEDIUM STORING CONTROL PROGRAM THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/915528 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6855 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283087.pdf [firstpage_image] =>[orig_patent_app_number] => 12915528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/915528
IMAGE FORMING APPARATUS, IMAGE FORMING METHOD, AND COMPUTER READABLE MEDIUM STORING CONTROL PROGRAM THEREFOR Oct 28, 2010 Abandoned
Array ( [id] => 8176585 [patent_doc_number] => 20120110303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Method for Process Synchronization of Embedded Applications in Multi-Core Systems' [patent_app_type] => utility [patent_app_number] => 12/913880 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110303.pdf [firstpage_image] =>[orig_patent_app_number] => 12913880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913880
Method for Process Synchronization of Embedded Applications in Multi-Core Systems Oct 27, 2010 Abandoned
Array ( [id] => 9834465 [patent_doc_number] => 08943299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Operating a stack of information in an information handling system' [patent_app_type] => utility [patent_app_number] => 12/817609 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7914 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12817609 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817609
Operating a stack of information in an information handling system Jun 16, 2010 Issued
Array ( [id] => 13974671 [patent_doc_number] => 10216692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Multi-core parallel processing system [patent_app_type] => utility [patent_app_number] => 12/817839 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2137 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12817839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817839
Multi-core parallel processing system Jun 16, 2010 Issued
Array ( [id] => 7658420 [patent_doc_number] => 20110307689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'PROCESSOR SUPPORT FOR HARDWARE TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 12/814025 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10236 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307689.pdf [firstpage_image] =>[orig_patent_app_number] => 12814025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/814025
Processor support for hardware transactional memory Jun 10, 2010 Issued
Array ( [id] => 7746845 [patent_doc_number] => 20120023312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'SUBPROCESSOR, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/258717 [patent_app_country] => US [patent_app_date] => 2010-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023312.pdf [firstpage_image] =>[orig_patent_app_number] => 13258717 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/258717
Subprocessor, integrated circuit device, and electronic apparatus Jun 9, 2010 Issued
Array ( [id] => 6584743 [patent_doc_number] => 20100235609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'RING-PATTERN BUS CONNECTED INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/720058 [patent_app_country] => US [patent_app_date] => 2010-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8788 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235609.pdf [firstpage_image] =>[orig_patent_app_number] => 12720058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/720058
Ring-pattern bus connected information processing apparatus, information processing method, and storage medium Mar 8, 2010 Issued
Array ( [id] => 6153633 [patent_doc_number] => 20110022821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'System and Methods to Improve Efficiency of VLIW Processors' [patent_app_type] => utility [patent_app_number] => 12/719823 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9227 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022821.pdf [firstpage_image] =>[orig_patent_app_number] => 12719823 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719823
System and Methods to Improve Efficiency of VLIW Processors Mar 7, 2010 Abandoned
Array ( [id] => 6094000 [patent_doc_number] => 20110219222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Building Approximate Data Dependences with a Moving Window' [patent_app_type] => utility [patent_app_number] => 12/717985 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 17851 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219222.pdf [firstpage_image] =>[orig_patent_app_number] => 12717985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717985
Building approximate data dependences with a moving window Mar 4, 2010 Issued
Array ( [id] => 9829366 [patent_doc_number] => 08938605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Instruction cracking based on machine state' [patent_app_type] => utility [patent_app_number] => 12/718685 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6088 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718685
Instruction cracking based on machine state Mar 4, 2010 Issued
Array ( [id] => 11680223 [patent_doc_number] => 09678754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'System and method of processing hierarchical very long instruction packets' [patent_app_type] => utility [patent_app_number] => 12/716359 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5641 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716359
System and method of processing hierarchical very long instruction packets Mar 2, 2010 Issued
Array ( [id] => 5940027 [patent_doc_number] => 20110213949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'METHODS AND APPARATUS FOR OPTIMIZING CONCURRENCY IN MULTIPLE CORE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/714810 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17892 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213949.pdf [firstpage_image] =>[orig_patent_app_number] => 12714810 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714810
METHODS AND APPARATUS FOR OPTIMIZING CONCURRENCY IN MULTIPLE CORE SYSTEMS Feb 28, 2010 Abandoned
Array ( [id] => 6050940 [patent_doc_number] => 20110208505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'ASSIGNING FLOATING-POINT OPERATIONS TO A FLOATING-POINT UNIT AND AN ARITHMETIC LOGIC UNIT' [patent_app_type] => utility [patent_app_number] => 12/711710 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20110208505.pdf [firstpage_image] =>[orig_patent_app_number] => 12711710 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711710
ASSIGNING FLOATING-POINT OPERATIONS TO A FLOATING-POINT UNIT AND AN ARITHMETIC LOGIC UNIT Feb 23, 2010 Abandoned
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