Search

Carlos Lugo

Examiner (ID: 6896, Phone: (571)272-7058 , Office: P/3675 )

Most Active Art Unit
3675
Art Unit(s)
3676, 3675, 3674, 3677, 3627, 3673
Total Applications
2136
Issued Applications
1455
Pending Applications
153
Abandoned Applications
552

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18320140 [patent_doc_number] => 20230118268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHODS AND APPARATUS FOR PREDICTING INSTRUCTIONS FOR EXECUTION [patent_app_type] => utility [patent_app_number] => 17/501257 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501257
Methods and apparatus for predicting instructions for execution Oct 13, 2021 Issued
Array ( [id] => 17535366 [patent_doc_number] => 20220113975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => VECTOR DATAFLOW ARCHITECTURE FOR EMBEDDED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/500017 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500017
Vector dataflow architecture for embedded systems Oct 12, 2021 Issued
Array ( [id] => 18174091 [patent_doc_number] => 11573801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-07 [patent_title] => Method and apparatus for executing vector instructions with merging behavior [patent_app_type] => utility [patent_app_number] => 17/489301 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/489301
Method and apparatus for executing vector instructions with merging behavior Sep 28, 2021 Issued
Array ( [id] => 18287092 [patent_doc_number] => 20230102564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PERMUTATION INSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/448816 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448816
Permutation instruction Sep 23, 2021 Issued
Array ( [id] => 20265770 [patent_doc_number] => 12436761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Instruction applicable to radix-3 butterfly computation [patent_app_type] => utility [patent_app_number] => 17/448828 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8776 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448828
Instruction applicable to radix-3 butterfly computation Sep 23, 2021 Issued
Array ( [id] => 18795965 [patent_doc_number] => 11829756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-28 [patent_title] => Vector cumulative sum instruction and circuit for implementing filtering operations [patent_app_type] => utility [patent_app_number] => 17/448871 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448871
Vector cumulative sum instruction and circuit for implementing filtering operations Sep 23, 2021 Issued
Array ( [id] => 18221916 [patent_doc_number] => 20230060910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DEPENDENCY SKIPPING EXECUTION [patent_app_type] => utility [patent_app_number] => 17/410230 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410230
Dependency skipping execution Aug 23, 2021 Issued
Array ( [id] => 18224085 [patent_doc_number] => 20230063079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SPECULATIVE RESOLUTION OF LAST BRANCH-ON-COUNT AT FETCH [patent_app_type] => utility [patent_app_number] => 17/410223 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410223
SPECULATIVE RESOLUTION OF LAST BRANCH-ON-COUNT AT FETCH Aug 23, 2021 Pending
Array ( [id] => 18207724 [patent_doc_number] => 20230053981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => INFERRING FUTURE VALUE FOR SPECULATIVE BRANCH RESOLUTION [patent_app_type] => utility [patent_app_number] => 17/406186 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406186
Inferring future value for speculative branch resolution Aug 18, 2021 Issued
Array ( [id] => 18195198 [patent_doc_number] => 20230048717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => UN-MARK INSTRUCTIONS ON AN INSTRUCTION MATCH TO REDUCE RESOURCES REQUIRED TO MATCH A GROUP OF INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/394367 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/394367
UN-MARK INSTRUCTIONS ON AN INSTRUCTION MATCH TO REDUCE RESOURCES REQUIRED TO MATCH A GROUP OF INSTRUCTIONS Aug 3, 2021 Pending
Array ( [id] => 19506930 [patent_doc_number] => 12118353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Performing load and permute with a single instruction in a system on a chip [patent_app_type] => utility [patent_app_number] => 17/391491 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 61 [patent_no_of_words] => 58076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391491
Performing load and permute with a single instruction in a system on a chip Aug 1, 2021 Issued
Array ( [id] => 20415640 [patent_doc_number] => 12498925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Register file structures combining vector and scalar data with global and local accesses [patent_app_type] => utility [patent_app_number] => 17/391143 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391143
Register file structures combining vector and scalar data with global and local accesses Aug 1, 2021 Issued
Array ( [id] => 18196543 [patent_doc_number] => 20230050062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 17/391395 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391395
SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP Aug 1, 2021 Abandoned
Array ( [id] => 18750205 [patent_doc_number] => 11809516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Apparatus and method for vector computing incorporating with matrix multiply and accumulation calculation [patent_app_type] => utility [patent_app_number] => 17/366485 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3882 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17366485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/366485
Apparatus and method for vector computing incorporating with matrix multiply and accumulation calculation Jul 1, 2021 Issued
Array ( [id] => 20537419 [patent_doc_number] => 12554496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Apparatus and method for configuring cooperative warps in vector computing system [patent_app_type] => utility [patent_app_number] => 17/366588 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17366588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/366588
Apparatus and method for configuring cooperative warps in vector computing system Jul 1, 2021 Issued
Array ( [id] => 19950385 [patent_doc_number] => 12321750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Entering protected pipeline mode with clearing [patent_app_type] => utility [patent_app_number] => 17/360646 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6337 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360646
Entering protected pipeline mode with clearing Jun 27, 2021 Issued
Array ( [id] => 18430373 [patent_doc_number] => 11675592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Instruction to query for model-dependent information [patent_app_type] => utility [patent_app_number] => 17/350326 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 24774 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350326
Instruction to query for model-dependent information Jun 16, 2021 Issued
Array ( [id] => 18342819 [patent_doc_number] => 11640297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Instruction and logic for systolic dot product with accumulate [patent_app_type] => utility [patent_app_number] => 17/304153 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 22435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304153
Instruction and logic for systolic dot product with accumulate Jun 14, 2021 Issued
Array ( [id] => 18038330 [patent_doc_number] => 20220382546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => APPARATUS AND METHOD FOR IMPLEMENTING VECTOR MASK IN VECTOR PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 17/334805 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334805
APPARATUS AND METHOD FOR IMPLEMENTING VECTOR MASK IN VECTOR PROCESSING UNIT May 30, 2021 Abandoned
Array ( [id] => 17230657 [patent_doc_number] => 20210357214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION [patent_app_type] => utility [patent_app_number] => 17/334901 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334901 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334901
Methods, apparatus, and instructions for user-level thread suspension May 30, 2021 Issued
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