Search

Carlos Lugo

Examiner (ID: 6896, Phone: (571)272-7058 , Office: P/3675 )

Most Active Art Unit
3675
Art Unit(s)
3676, 3675, 3674, 3677, 3627, 3673
Total Applications
2136
Issued Applications
1455
Pending Applications
153
Abandoned Applications
552

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17877325 [patent_doc_number] => 11449338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Handling exceptions in a multi-tile processing arrangement [patent_app_type] => utility [patent_app_number] => 16/395386 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 14100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395386
Handling exceptions in a multi-tile processing arrangement Apr 25, 2019 Issued
Array ( [id] => 16972295 [patent_doc_number] => 11068267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => High bandwidth logical register flush recovery [patent_app_type] => utility [patent_app_number] => 16/392722 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/392722
High bandwidth logical register flush recovery Apr 23, 2019 Issued
Array ( [id] => 17605866 [patent_doc_number] => 11334354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Predication methods for vector processors [patent_app_type] => utility [patent_app_number] => 16/361449 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6147 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16361449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/361449
Predication methods for vector processors Mar 21, 2019 Issued
Array ( [id] => 16178986 [patent_doc_number] => 20200225954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => REGISTER RENAMING OF A SHAREABLE INSTRUCTION OPERAND CACHE [patent_app_type] => utility [patent_app_number] => 16/294916 [patent_app_country] => US [patent_app_date] => 2019-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/294916
Register renaming of a shareable instruction operand cache Mar 5, 2019 Issued
Array ( [id] => 17636783 [patent_doc_number] => 11347507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Secure control flow prediction [patent_app_type] => utility [patent_app_number] => 16/241455 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11514 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241455 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241455
Secure control flow prediction Jan 6, 2019 Issued
Array ( [id] => 15685557 [patent_doc_number] => 20200097442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => EFFICIENT UTILIZATION OF SYSTOLIC ARRAYS IN COMPUTATIONAL PROCESSING [patent_app_type] => utility [patent_app_number] => 16/241085 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241085
Efficient utilization of systolic arrays in computational processing Jan 6, 2019 Issued
Array ( [id] => 14539041 [patent_doc_number] => 20190205142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => SYSTEMS AND METHODS FOR SECURE PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/240004 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240004
SYSTEMS AND METHODS FOR SECURE PROCESSOR Jan 3, 2019 Abandoned
Array ( [id] => 16116317 [patent_doc_number] => 20200210181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR VECTOR ELEMENT SORTING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/236445 [patent_app_country] => US [patent_app_date] => 2018-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236445
APPARATUSES, METHODS, AND SYSTEMS FOR VECTOR ELEMENT SORTING INSTRUCTIONS Dec 28, 2018 Abandoned
Array ( [id] => 16910342 [patent_doc_number] => 11042381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Register renaming-based techniques for block-based processors [patent_app_type] => utility [patent_app_number] => 16/214040 [patent_app_country] => US [patent_app_date] => 2018-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214040 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214040
Register renaming-based techniques for block-based processors Dec 7, 2018 Issued
Array ( [id] => 16879813 [patent_doc_number] => 11029960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Apparatus and method for widened SIMD execution within a constrained register file [patent_app_type] => utility [patent_app_number] => 16/214012 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 18531 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214012
Apparatus and method for widened SIMD execution within a constrained register file Dec 6, 2018 Issued
Array ( [id] => 16017685 [patent_doc_number] => 20200183686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => HARDWARE ACCELERATOR WITH LOCALLY STORED MACROS [patent_app_type] => utility [patent_app_number] => 16/211820 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211820
Hardware accelerator with locally stored macros Dec 5, 2018 Issued
Array ( [id] => 16017713 [patent_doc_number] => 20200183700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => LOGICAL REGISTER RECOVERY WITHIN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/210349 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210349
Logical register recovery within a processor Dec 4, 2018 Issued
Array ( [id] => 15966813 [patent_doc_number] => 20200167158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => COMPOUND INSTRUCTION SET ARCHITECTURE FOR A NEURAL INFERENCE CHIP [patent_app_type] => utility [patent_app_number] => 16/202871 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202871
Compound instruction set architecture for a neural inference chip Nov 27, 2018 Issued
Array ( [id] => 15966829 [patent_doc_number] => 20200167166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => DUAL COMPARE OF LEAST-SIGNIFICANT-BIT FOR DEPENDENCY WAKE UP FROM A FUSED INSTRUCTION TAG IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 16/202489 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202489 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202489
Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor Nov 27, 2018 Issued
Array ( [id] => 15870587 [patent_doc_number] => 20200142697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => INSTRUCTION COMPLETION TABLE WITH READY-TO-COMPLETE VECTOR [patent_app_type] => utility [patent_app_number] => 16/182760 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182760 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182760
Instruction completion table with ready-to-complete vector Nov 6, 2018 Issued
Array ( [id] => 14282051 [patent_doc_number] => 20190138310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => METHOD FOR READING OUT VARIABLES FROM AN FPGA [patent_app_type] => utility [patent_app_number] => 16/182637 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182637 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182637
METHOD FOR READING OUT VARIABLES FROM AN FPGA Nov 6, 2018 Abandoned
Array ( [id] => 18015342 [patent_doc_number] => 11507640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Apparatus and methods for vector operations [patent_app_type] => utility [patent_app_number] => 16/172653 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6627 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16172653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/172653
Apparatus and methods for vector operations Oct 25, 2018 Issued
Array ( [id] => 14314197 [patent_doc_number] => 20190146802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => INFORMATION PROCESSING APPARATUS, ARITHMETIC PROCESSING APPARATUS, AND CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/167587 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167587
INFORMATION PROCESSING APPARATUS, ARITHMETIC PROCESSING APPARATUS, AND CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS Oct 22, 2018 Abandoned
Array ( [id] => 17194809 [patent_doc_number] => 11163562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Processing unit and operating method therefor [patent_app_type] => utility [patent_app_number] => 16/154852 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 20783 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154852
Processing unit and operating method therefor Oct 8, 2018 Issued
Array ( [id] => 15743445 [patent_doc_number] => 20200110611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => APPARATUS AND METHOD FOR PERFORMING MULTIPLE CONTROL FLOW PREDICTIONS [patent_app_type] => utility [patent_app_number] => 16/155049 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155049 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155049
Apparatus and method for performing multiple control flow predictions Oct 8, 2018 Issued
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