Search

Carlos R Ortiz Rodriguez

Examiner (ID: 5168, Phone: (571)272-3766 , Office: P/2127 )

Most Active Art Unit
2119
Art Unit(s)
2127, 2122, 2119, 2123, 2125
Total Applications
923
Issued Applications
646
Pending Applications
78
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17395866 [patent_doc_number] => 11244890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Ground via clustering for crosstalk mitigation [patent_app_type] => utility [patent_app_number] => 17/074820 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074820
Ground via clustering for crosstalk mitigation Oct 19, 2020 Issued
Array ( [id] => 16625099 [patent_doc_number] => 20210043752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/068769 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068769
Semiconductor device Oct 11, 2020 Issued
Array ( [id] => 17818545 [patent_doc_number] => 11424167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/067565 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067565
Semiconductor package structure and method for manufacturing the same Oct 8, 2020 Issued
Array ( [id] => 17574094 [patent_doc_number] => 11322368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Method for fabricating semiconductor package [patent_app_type] => utility [patent_app_number] => 17/037003 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037003
Method for fabricating semiconductor package Sep 28, 2020 Issued
Array ( [id] => 17529900 [patent_doc_number] => 11302598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/034589 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034589
Semiconductor package Sep 27, 2020 Issued
Array ( [id] => 17509236 [patent_doc_number] => 20220102339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 17/033513 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033513
GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY Sep 24, 2020 Pending
Array ( [id] => 17424332 [patent_doc_number] => 11257794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/030588 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030588
Semiconductor package and method of manufacturing the same Sep 23, 2020 Issued
Array ( [id] => 17971394 [patent_doc_number] => 11488943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Modules with integrated circuits and devices [patent_app_type] => utility [patent_app_number] => 17/030347 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 108 [patent_no_of_words] => 30804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030347
Modules with integrated circuits and devices Sep 22, 2020 Issued
Array ( [id] => 17878631 [patent_doc_number] => 11450655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/021917 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 13182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021917
Display device and method of manufacturing the same Sep 14, 2020 Issued
Array ( [id] => 16545071 [patent_doc_number] => 20200411486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => METHOD TO FORM A 3D SEMICONDUCTOR DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/020766 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020766
Method to form a 3D semiconductor device and structure Sep 13, 2020 Issued
Array ( [id] => 18120630 [patent_doc_number] => 11552029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Semiconductor devices with reinforced substrates [patent_app_type] => utility [patent_app_number] => 17/013321 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6970 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013321
Semiconductor devices with reinforced substrates Sep 3, 2020 Issued
Array ( [id] => 17456124 [patent_doc_number] => 11270991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods [patent_app_type] => utility [patent_app_number] => 17/010001 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 11391 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010001
Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods Sep 1, 2020 Issued
Array ( [id] => 18032078 [patent_doc_number] => 11515276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Integrated circuit, package structure, and manufacturing method of package structure [patent_app_type] => utility [patent_app_number] => 17/006879 [patent_app_country] => US [patent_app_date] => 2020-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 8769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006879
Integrated circuit, package structure, and manufacturing method of package structure Aug 29, 2020 Issued
Array ( [id] => 16487906 [patent_doc_number] => 20200381515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/997886 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997886
Semiconductor device and method of manufacturing semiconductor device Aug 18, 2020 Issued
Array ( [id] => 17493511 [patent_doc_number] => 11282828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => High density architecture design for 3D logic and 3D memory circuits [patent_app_type] => utility [patent_app_number] => 16/997525 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 62 [patent_no_of_words] => 3670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997525 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997525
High density architecture design for 3D logic and 3D memory circuits Aug 18, 2020 Issued
Array ( [id] => 17318914 [patent_doc_number] => 20210407964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH IMPROVED THERMAL PERFORMANCE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/939449 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939449
Semiconductor device assemblies and systems with improved thermal performance and methods for making the same Jul 26, 2020 Issued
Array ( [id] => 17025526 [patent_doc_number] => 20210249398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => METHODS OF MANUFACTURING LIGHT-EMITTING DEVICES WITH METAL INLAYS AND BOTTOM CONTACTS [patent_app_type] => utility [patent_app_number] => 16/934911 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934911
Methods of manufacturing light-emitting devices with metal inlays and bottom contacts Jul 20, 2020 Issued
Array ( [id] => 16425197 [patent_doc_number] => 20200350395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT [patent_app_type] => utility [patent_app_number] => 16/933062 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933062
Semiconductor device structure with magnetic element Jul 19, 2020 Issued
Array ( [id] => 16402371 [patent_doc_number] => 20200343229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => IMAGE DISPLAY DEVICE AND DISPLAY [patent_app_type] => utility [patent_app_number] => 16/925184 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925184 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925184
Image display device and display Jul 8, 2020 Issued
Array ( [id] => 17130404 [patent_doc_number] => 20210305173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/917920 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917920 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917920
Package structure and fabricating method thereof Jun 30, 2020 Issued
Menu