Search

Carlos R Ortiz Rodriguez

Examiner (ID: 5168, Phone: (571)272-3766 , Office: P/2127 )

Most Active Art Unit
2119
Art Unit(s)
2127, 2122, 2119, 2123, 2125
Total Applications
923
Issued Applications
646
Pending Applications
78
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17232682 [patent_doc_number] => 20210359239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE AND LIGHTING APPARATUS FOR VEHICLES USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/386116 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -47 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386116
Organic light emitting display device and lighting apparatus for vehicles using the same Jul 26, 2021 Issued
Array ( [id] => 18563171 [patent_doc_number] => 11728426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Ferroelectric MFM inductor and related circuits [patent_app_type] => utility [patent_app_number] => 17/385804 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 7385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385804
Ferroelectric MFM inductor and related circuits Jul 25, 2021 Issued
Array ( [id] => 18595182 [patent_doc_number] => 11744104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Display panel and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/385791 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 11119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385791
Display panel and electronic device including the same Jul 25, 2021 Issued
Array ( [id] => 18161517 [patent_doc_number] => 20230028109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION METHOD FOR SEMICONDUCTOR DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 17/382751 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382751
Semiconductor chip, semiconductor device and electrostatic discharge protection method for semiconductor device thereof Jul 21, 2021 Issued
Array ( [id] => 19183850 [patent_doc_number] => 11990451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method for packaging semiconductor, semiconductor package structure, and package [patent_app_type] => utility [patent_app_number] => 17/372530 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372530
Method for packaging semiconductor, semiconductor package structure, and package Jul 11, 2021 Issued
Array ( [id] => 19183850 [patent_doc_number] => 11990451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method for packaging semiconductor, semiconductor package structure, and package [patent_app_type] => utility [patent_app_number] => 17/372530 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372530
Method for packaging semiconductor, semiconductor package structure, and package Jul 11, 2021 Issued
Array ( [id] => 19183850 [patent_doc_number] => 11990451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method for packaging semiconductor, semiconductor package structure, and package [patent_app_type] => utility [patent_app_number] => 17/372530 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372530
Method for packaging semiconductor, semiconductor package structure, and package Jul 11, 2021 Issued
Array ( [id] => 19183850 [patent_doc_number] => 11990451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method for packaging semiconductor, semiconductor package structure, and package [patent_app_type] => utility [patent_app_number] => 17/372530 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372530
Method for packaging semiconductor, semiconductor package structure, and package Jul 11, 2021 Issued
Array ( [id] => 18481219 [patent_doc_number] => 11694974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor die with warpage release layer structure in package and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 17/370299 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 9527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370299
Semiconductor die with warpage release layer structure in package and fabricating method thereof Jul 7, 2021 Issued
Array ( [id] => 17188797 [patent_doc_number] => 20210335682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => METHOD FOR PRODUCING POWER SEMICONDUCTOR MODULE ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/366870 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17366870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/366870
Method for producing power semiconductor module arrangement Jul 1, 2021 Issued
Array ( [id] => 18431757 [patent_doc_number] => 11676989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Display device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/366976 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17366976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/366976
Display device and method for manufacturing the same Jul 1, 2021 Issued
Array ( [id] => 18608183 [patent_doc_number] => 11749661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Package comprising a substrate and a multi-capacitor integrated passive device [patent_app_type] => utility [patent_app_number] => 17/364318 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13090 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364318
Package comprising a substrate and a multi-capacitor integrated passive device Jun 29, 2021 Issued
Array ( [id] => 17448383 [patent_doc_number] => 20220068888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => DIE TO DIE INTERFACE CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/363121 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363121
Die to die interface circuit Jun 29, 2021 Issued
Array ( [id] => 18120648 [patent_doc_number] => 11552047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Semiconductor package including plurality of semiconductor chips and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/360173 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 12754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360173
Semiconductor package including plurality of semiconductor chips and method for manufacturing the same Jun 27, 2021 Issued
Array ( [id] => 17870860 [patent_doc_number] => 20220293597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR AND CIRCUIT STRUCTURES, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/357803 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357803
Semiconductor and circuit structures, and related methods Jun 23, 2021 Issued
Array ( [id] => 17130491 [patent_doc_number] => 20210305260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SRAM Circuits with Aligned Gate Electrodes [patent_app_type] => utility [patent_app_number] => 17/345309 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345309
SRAM circuits with aligned gate electrodes Jun 10, 2021 Issued
Array ( [id] => 18190641 [patent_doc_number] => 11581242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Integrated high efficiency gate on gate cooling [patent_app_type] => utility [patent_app_number] => 17/344259 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4173 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344259
Integrated high efficiency gate on gate cooling Jun 9, 2021 Issued
Array ( [id] => 18608190 [patent_doc_number] => 11749668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => PSPI-based patterning method for RDL [patent_app_type] => utility [patent_app_number] => 17/343402 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 5269 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343402 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343402
PSPI-based patterning method for RDL Jun 8, 2021 Issued
Array ( [id] => 17536683 [patent_doc_number] => 20220115292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR CHIPS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/341463 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341463
Semiconductor chips and semiconductor packages including the same Jun 7, 2021 Issued
Array ( [id] => 18448362 [patent_doc_number] => 11683954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Flexible display apparatus [patent_app_type] => utility [patent_app_number] => 17/341164 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341164
Flexible display apparatus Jun 6, 2021 Issued
Menu