Search

Carol M Koslow

Examiner (ID: 18210)

Most Active Art Unit
1734
Art Unit(s)
1754, 1734, 1755, 1108, 1793
Total Applications
4883
Issued Applications
3887
Pending Applications
233
Abandoned Applications
725

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10550336 [patent_doc_number] => 09274961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Method for building multi-processor system with nodes having multiple cache coherency domains' [patent_app_type] => utility [patent_app_number] => 14/534842 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6813 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 815 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14534842 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/534842
Method for building multi-processor system with nodes having multiple cache coherency domains Nov 5, 2014 Issued
Array ( [id] => 10215861 [patent_doc_number] => 20150100853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'APPARATUSES AND METHODS FOR STORING VALIDITY MASKS AND OPERATING APPARATUSES' [patent_app_type] => utility [patent_app_number] => 14/520732 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4743 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/520732
Apparatuses and methods for storing validity masks and operating apparatuses Oct 21, 2014 Issued
Array ( [id] => 9967805 [patent_doc_number] => 09015439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-21 [patent_title] => 'Event lock storage device' [patent_app_type] => utility [patent_app_number] => 14/292047 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9781 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292047
Event lock storage device May 29, 2014 Issued
Array ( [id] => 10188722 [patent_doc_number] => 09218141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Managing write operations to an extent of tracks migrated between storage devices' [patent_app_type] => utility [patent_app_number] => 14/169150 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169150 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/169150
Managing write operations to an extent of tracks migrated between storage devices Jan 29, 2014 Issued
Array ( [id] => 10847635 [patent_doc_number] => 08874835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'Data placement based on data properties in a tiered storage device system' [patent_app_type] => utility [patent_app_number] => 14/157481 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13382 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157481 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/157481
Data placement based on data properties in a tiered storage device system Jan 15, 2014 Issued
Array ( [id] => 10589395 [patent_doc_number] => 09311007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Configuring registers into low power conditions' [patent_app_type] => utility [patent_app_number] => 14/138729 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5115 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138729 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138729
Configuring registers into low power conditions Dec 22, 2013 Issued
Array ( [id] => 9599061 [patent_doc_number] => 20140195742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SYSTEM ON CHIP INCLUDING MEMORY MANAGEMENT UNIT AND MEMORY ADDRESS TRANSLATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/138982 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9078 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138982 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138982
System on chip including memory management unit and memory address translation method thereof Dec 22, 2013 Issued
Array ( [id] => 9571564 [patent_doc_number] => 20140189278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'METHOD AND APPARATUS FOR ALLOCATING MEMORY SPACE WITH WRITE-COMBINE ATTRIBUTE' [patent_app_type] => utility [patent_app_number] => 14/102061 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14019 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102061 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102061
Method and apparatus for allocating memory space with write-combine attribute Dec 9, 2013 Issued
Array ( [id] => 9398386 [patent_doc_number] => 20140095792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/097306 [patent_app_country] => US [patent_app_date] => 2013-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7618 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097306 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/097306
CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD Dec 4, 2013 Abandoned
Array ( [id] => 9386104 [patent_doc_number] => 20140089587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'PROCESSOR, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/096082 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 20475 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096082 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096082
PROCESSOR, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF PROCESSOR Dec 3, 2013 Abandoned
Array ( [id] => 10609971 [patent_doc_number] => 09330004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Data processing method, cache node, collaboration controller, and system' [patent_app_type] => utility [patent_app_number] => 14/094148 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 11787 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14094148 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/094148
Data processing method, cache node, collaboration controller, and system Dec 1, 2013 Issued
Array ( [id] => 10210562 [patent_doc_number] => 20150095553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'SELECTIVE SOFTWARE-BASED DATA COMPRESSION IN A STORAGE SYSTEM BASED ON DATA HEAT' [patent_app_type] => utility [patent_app_number] => 14/043522 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043522
SELECTIVE SOFTWARE-BASED DATA COMPRESSION IN A STORAGE SYSTEM BASED ON DATA HEAT Sep 30, 2013 Abandoned
Array ( [id] => 9814446 [patent_doc_number] => 20150026391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'BLOCK GROUPING METHOD FOR GARBAGE COLLECTION OF SOLID STATE DRIVE' [patent_app_type] => utility [patent_app_number] => 14/042808 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4390 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042808 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042808
Block grouping method for garbage collection of solid state drive Sep 30, 2013 Issued
Array ( [id] => 9903475 [patent_doc_number] => 20150058675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SOFTWARE UNIT TEST IMMUNITY INDEX' [patent_app_type] => utility [patent_app_number] => 13/971001 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10132 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971001 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971001
Software unit test immunity index Aug 19, 2013 Issued
Array ( [id] => 9903351 [patent_doc_number] => 20150058551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'PICO ENGINE POOL TRANSACTIONAL MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/970601 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970601 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/970601
Picoengine pool transactional memory architecture Aug 19, 2013 Issued
Array ( [id] => 9637032 [patent_doc_number] => 20140215141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'High-Speed Processor Core Comprising Mapped Auxilliary Component Functionality' [patent_app_type] => utility [patent_app_number] => 13/965810 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7033 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965810 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965810
High-Speed Processor Core Comprising Mapped Auxilliary Component Functionality Aug 12, 2013 Abandoned
Array ( [id] => 9940654 [patent_doc_number] => 08990485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Memory pre-characterization' [patent_app_type] => utility [patent_app_number] => 13/917396 [patent_app_country] => US [patent_app_date] => 2013-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8855 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13917396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/917396
Memory pre-characterization Jun 12, 2013 Issued
Array ( [id] => 10530397 [patent_doc_number] => 09256533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Adjustment of destage rate based on read and write response time requirements' [patent_app_type] => utility [patent_app_number] => 13/790460 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6297 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790460
Adjustment of destage rate based on read and write response time requirements Mar 7, 2013 Issued
Array ( [id] => 9193358 [patent_doc_number] => 20130332673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'SELECTING A VIRTUAL TAPE SERVER IN A STORAGE SYSTEM TO PROVIDE DATA COPY WHILE MINIMIZING SYSTEM JOB LOAD' [patent_app_type] => utility [patent_app_number] => 13/789275 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789275
Selecting a virtual tape server in a storage system to provide data copy while minimizing system job load Mar 6, 2013 Issued
Array ( [id] => 8929503 [patent_doc_number] => 20130185263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'SELF LEARNING BACKUP AND RECOVERY MANAGEMENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/727453 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5088 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727453
Self learning backup and recovery management system Dec 25, 2012 Issued
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