Search

Carol Rademaker

Examiner (ID: 7369)

Most Active Art Unit
2912
Art Unit(s)
2900, 2912
Total Applications
2914
Issued Applications
2884
Pending Applications
0
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17674721 [patent_doc_number] => 20220187888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => CONFIGURABLE VRM CARD [patent_app_type] => utility [patent_app_number] => 17/120139 [patent_app_country] => US [patent_app_date] => 2020-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120139
Configurable VRM card Dec 11, 2020 Issued
Array ( [id] => 18135898 [patent_doc_number] => 11561570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Apparatus and methods for low power frequency clock generation and distribution [patent_app_type] => utility [patent_app_number] => 17/108152 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108152
Apparatus and methods for low power frequency clock generation and distribution Nov 30, 2020 Issued
Array ( [id] => 18111327 [patent_doc_number] => 20230004207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => CONTROL DEVICE AND DATA PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/781172 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/781172
Control device and data processing system Nov 24, 2020 Issued
Array ( [id] => 17715256 [patent_doc_number] => 11379247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Methods and systems for comparing computer configuration information [patent_app_type] => utility [patent_app_number] => 17/104799 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3616 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104799
Methods and systems for comparing computer configuration information Nov 24, 2020 Issued
Array ( [id] => 17580832 [patent_doc_number] => 20220137687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => TWO-STAGE DYNAMIC POWER SUPPLY VOLTAGE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/085505 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085505
Two-stage dynamic power supply voltage adjustment Oct 29, 2020 Issued
Array ( [id] => 16625488 [patent_doc_number] => 20210044141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => PARALLEL OUTPUT OF BACKUP POWER MODULES [patent_app_type] => utility [patent_app_number] => 17/077002 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077002
PARALLEL OUTPUT OF BACKUP POWER MODULES Oct 21, 2020 Abandoned
Array ( [id] => 17552321 [patent_doc_number] => 20220123664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => POWER SUPPLY UNITS AND METHODS FOR MANAGING OPERATION OF SAME [patent_app_type] => utility [patent_app_number] => 17/073260 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073260
System and method for detecting the presence of input power of different types Oct 15, 2020 Issued
Array ( [id] => 18493253 [patent_doc_number] => 11698668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Information processing apparatus and control method for selectively supplying power and clocks to module circuits used for verification [patent_app_type] => utility [patent_app_number] => 17/067224 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067224
Information processing apparatus and control method for selectively supplying power and clocks to module circuits used for verification Oct 8, 2020 Issued
Array ( [id] => 19122269 [patent_doc_number] => 11966251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Device for generating a supply/bias voltage and a clock signal for a synchronous digital circuit [patent_app_type] => utility [patent_app_number] => 17/765749 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 13316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17765749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/765749
Device for generating a supply/bias voltage and a clock signal for a synchronous digital circuit Sep 27, 2020 Issued
Array ( [id] => 16856644 [patent_doc_number] => 20210157389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => STANDBY CURRENT REDUCTION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/034154 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034154
Standby current reduction in memory devices Sep 27, 2020 Issued
Array ( [id] => 17325397 [patent_doc_number] => 11216409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Providing access from outside a multicore processor SoC to individually configure voltages [patent_app_type] => utility [patent_app_number] => 17/025992 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025992
Providing access from outside a multicore processor SoC to individually configure voltages Sep 17, 2020 Issued
Array ( [id] => 18275827 [patent_doc_number] => 11614770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions [patent_app_type] => utility [patent_app_number] => 17/023145 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023145
Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions Sep 15, 2020 Issued
Array ( [id] => 18644544 [patent_doc_number] => 11768611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Secure boot of a processing chip [patent_app_type] => utility [patent_app_number] => 17/006717 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 73893 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006717
Secure boot of a processing chip Aug 27, 2020 Issued
Array ( [id] => 17651191 [patent_doc_number] => 11353917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Generating globally coherent timestamps [patent_app_type] => utility [patent_app_number] => 16/992673 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992673
Generating globally coherent timestamps Aug 12, 2020 Issued
Array ( [id] => 17706548 [patent_doc_number] => 20220206554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => PROCESSOR AND POWER SUPPLY RIPPLE REDUCTION METHOD [patent_app_type] => utility [patent_app_number] => 17/623603 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/623603
PROCESSOR AND POWER SUPPLY RIPPLE REDUCTION METHOD Aug 12, 2020 Abandoned
Array ( [id] => 17408657 [patent_doc_number] => 11249537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => USB type-C power delivery management [patent_app_type] => utility [patent_app_number] => 16/927649 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927649 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927649
USB type-C power delivery management Jul 12, 2020 Issued
Array ( [id] => 17047048 [patent_doc_number] => 11100230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-24 [patent_title] => Modular embedded chassis with firmware for removably coupled compute devices, and methods and systems for the same [patent_app_type] => utility [patent_app_number] => 16/921554 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7118 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921554
Modular embedded chassis with firmware for removably coupled compute devices, and methods and systems for the same Jul 5, 2020 Issued
Array ( [id] => 19924553 [patent_doc_number] => 12298833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Performance level control in a data processing apparatus [patent_app_type] => utility [patent_app_number] => 18/007627 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5427 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18007627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/007627
Performance level control in a data processing apparatus Jun 25, 2020 Issued
Array ( [id] => 18121467 [patent_doc_number] => 11552871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Receive-side timestamp accuracy [patent_app_type] => utility [patent_app_number] => 16/900931 [patent_app_country] => US [patent_app_date] => 2020-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900931 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900931
Receive-side timestamp accuracy Jun 13, 2020 Issued
Array ( [id] => 17260919 [patent_doc_number] => 20210373904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => OPERATING SYSTEM INSTALLATION MECHANISM [patent_app_type] => utility [patent_app_number] => 16/885381 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885381
Operating system installation mechanism May 27, 2020 Issued
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