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Caroline Koestner

Examiner (ID: 12183)

Most Active Art Unit
1102
Art Unit(s)
1102
Total Applications
74
Issued Applications
68
Pending Applications
0
Abandoned Applications
6

Applications

Application numberTitle of the applicationFiling DateStatus
90/003141 HIGH POWER MOSFET WITH LOW ON-RESISTANCE AND HIGH BREAKDOWN VOLTAGE Jul 25, 1993 Issued
Array ( [id] => 2845105 [patent_doc_number] => 05106778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Vertical transistor device fabricated with semiconductor regrowth' [patent_app_type] => 1 [patent_app_number] => 7/481860 [patent_app_country] => US [patent_app_date] => 1990-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4565 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/106/05106778.pdf [firstpage_image] =>[orig_patent_app_number] => 481860 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/481860
Vertical transistor device fabricated with semiconductor regrowth Feb 15, 1990 Issued
Array ( [id] => 2860327 [patent_doc_number] => 05082793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-21 [patent_title] => 'Method for making solid state device utilizing ion implantation techniques' [patent_app_type] => 1 [patent_app_number] => 7/438692 [patent_app_country] => US [patent_app_date] => 1989-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 9 [patent_no_of_words] => 7990 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/082/05082793.pdf [firstpage_image] =>[orig_patent_app_number] => 438692 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/438692
Method for making solid state device utilizing ion implantation techniques Nov 16, 1989 Issued
Array ( [id] => 2852263 [patent_doc_number] => 05134090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Method of fabricating patterned epitaxial silicon films utilizing molecular beam epitaxy' [patent_app_type] => 1 [patent_app_number] => 7/366222 [patent_app_country] => US [patent_app_date] => 1989-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 13 [patent_no_of_words] => 2948 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134090.pdf [firstpage_image] =>[orig_patent_app_number] => 366222 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366222
Method of fabricating patterned epitaxial silicon films utilizing molecular beam epitaxy Jun 11, 1989 Issued
Array ( [id] => 2468863 [patent_doc_number] => 04878956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-07 [patent_title] => 'Single crystal films of cubic group II fluorides on semiconductor compounds' [patent_app_type] => 1 [patent_app_number] => 7/320884 [patent_app_country] => US [patent_app_date] => 1989-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3585 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/878/04878956.pdf [firstpage_image] =>[orig_patent_app_number] => 320884 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/320884
Single crystal films of cubic group II fluorides on semiconductor compounds Mar 8, 1989 Issued
Array ( [id] => 2871331 [patent_doc_number] => 05091333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth' [patent_app_type] => 1 [patent_app_number] => 7/241506 [patent_app_country] => US [patent_app_date] => 1988-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2493 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091333.pdf [firstpage_image] =>[orig_patent_app_number] => 241506 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/241506
Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth Sep 6, 1988 Issued
Array ( [id] => 2551144 [patent_doc_number] => 04833095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-23 [patent_title] => 'Method for buried channel field effect transistor for microwave and millimeter frequencies utilizing ion implantation' [patent_app_type] => 1 [patent_app_number] => 7/128882 [patent_app_country] => US [patent_app_date] => 1987-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 5919 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/833/04833095.pdf [firstpage_image] =>[orig_patent_app_number] => 128882 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/128882
Method for buried channel field effect transistor for microwave and millimeter frequencies utilizing ion implantation Dec 3, 1987 Issued
90/001306 EPITAXIAL WAFER FOR USE IN PRODUCTION OF LIGHT EMITTING DIODE Aug 9, 1987 Issued
Array ( [id] => 2747423 [patent_doc_number] => 05037774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-06 [patent_title] => 'Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon' [patent_app_type] => 1 [patent_app_number] => 7/073839 [patent_app_country] => US [patent_app_date] => 1987-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 5521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/037/05037774.pdf [firstpage_image] =>[orig_patent_app_number] => 073839 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/073839
Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon Jul 14, 1987 Issued
Array ( [id] => 2732925 [patent_doc_number] => 05032538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'Semiconductor embedded layer technology utilizing selective epitaxial growth methods' [patent_app_type] => 1 [patent_app_number] => 7/073912 [patent_app_country] => US [patent_app_date] => 1987-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 94 [patent_no_of_words] => 17001 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/032/05032538.pdf [firstpage_image] =>[orig_patent_app_number] => 073912 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/073912
Semiconductor embedded layer technology utilizing selective epitaxial growth methods Jul 6, 1987 Issued
Array ( [id] => 2519038 [patent_doc_number] => 04861393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-29 [patent_title] => 'Semiconductor heterostructures having Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy' [patent_app_type] => 1 [patent_app_number] => 7/057679 [patent_app_country] => US [patent_app_date] => 1987-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3723 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/861/04861393.pdf [firstpage_image] =>[orig_patent_app_number] => 057679 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/057679
Semiconductor heterostructures having Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy May 27, 1987 Issued
Array ( [id] => 2685302 [patent_doc_number] => RE033671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-20 [patent_title] => 'Method of making high mobility multilayered heterojunction device employing modulated doping' [patent_app_type] => 2 [patent_app_number] => 7/058668 [patent_app_country] => US [patent_app_date] => 1987-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4284 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/033/RE033671.pdf [firstpage_image] =>[orig_patent_app_number] => 058668 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/058668
Method of making high mobility multilayered heterojunction device employing modulated doping May 25, 1987 Issued
Array ( [id] => 2456641 [patent_doc_number] => 04784963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-15 [patent_title] => 'Method for light-induced photolytic deposition simultaneously independently controlling at least two different frequency radiations during the process' [patent_app_type] => 1 [patent_app_number] => 7/048965 [patent_app_country] => US [patent_app_date] => 1987-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3981 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/784/04784963.pdf [firstpage_image] =>[orig_patent_app_number] => 048965 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/048965
Method for light-induced photolytic deposition simultaneously independently controlling at least two different frequency radiations during the process May 10, 1987 Issued
Array ( [id] => 2516530 [patent_doc_number] => 04870032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-26 [patent_title] => 'Method of fabricating single crystal films of cubic group II fluorides on semiconductor componds by molecular beam epitaxy' [patent_app_type] => 1 [patent_app_number] => 7/029844 [patent_app_country] => US [patent_app_date] => 1987-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/870/04870032.pdf [firstpage_image] =>[orig_patent_app_number] => 029844 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/029844
Method of fabricating single crystal films of cubic group II fluorides on semiconductor componds by molecular beam epitaxy Mar 23, 1987 Issued
07/006989 SINGLE CRYSTAL FILMS ON SEMICONDUCTOR COMPOUNDS Jan 13, 1987 Abandoned
06/935164 METHOD OF FABRICATING PATTERNED EPITAXIAL SILICON FILMS AND DEVICES MADE THEREBY Nov 24, 1986 Abandoned
06/910001 REDUCING DISLOCATIONS IN SEMICONDUCTORS Sep 21, 1986 Abandoned
Array ( [id] => 2511255 [patent_doc_number] => 04851364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'Method of forming well regions for field effect transistors utilizing self-aligned techniques' [patent_app_type] => 1 [patent_app_number] => 6/850037 [patent_app_country] => US [patent_app_date] => 1986-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 54 [patent_no_of_words] => 20751 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/851/04851364.pdf [firstpage_image] =>[orig_patent_app_number] => 850037 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/850037
Method of forming well regions for field effect transistors utilizing self-aligned techniques Apr 9, 1986 Issued
Array ( [id] => 2508101 [patent_doc_number] => 04830971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'Method for manufacturing a semiconductor device utilizing self-aligned contact regions' [patent_app_type] => 1 [patent_app_number] => 6/832647 [patent_app_country] => US [patent_app_date] => 1986-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 36 [patent_no_of_words] => 7513 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/830/04830971.pdf [firstpage_image] =>[orig_patent_app_number] => 832647 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/832647
Method for manufacturing a semiconductor device utilizing self-aligned contact regions Feb 24, 1986 Issued
Array ( [id] => 2415516 [patent_doc_number] => 04746623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-24 [patent_title] => 'Method of making bipolar semiconductor device with wall spacer' [patent_app_type] => 1 [patent_app_number] => 6/809653 [patent_app_country] => US [patent_app_date] => 1986-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1334 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/746/04746623.pdf [firstpage_image] =>[orig_patent_app_number] => 809653 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/809653
Method of making bipolar semiconductor device with wall spacer Jan 28, 1986 Issued
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