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Caroline Koestner

Examiner (ID: 12183)

Most Active Art Unit
1102
Art Unit(s)
1102
Total Applications
74
Issued Applications
68
Pending Applications
0
Abandoned Applications
6

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2001336 [patent_doc_number] => 04398339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-08-16 [patent_title] => 'Fabrication method for high power MOS device' [patent_app_type] => 1 [patent_app_number] => 6/300474 [patent_app_country] => US [patent_app_date] => 1981-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5179 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/398/04398339.pdf [firstpage_image] =>[orig_patent_app_number] => 300474 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/300474
Fabrication method for high power MOS device Sep 8, 1981 Issued
Array ( [id] => 2120311 [patent_doc_number] => 04425700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-17 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 6/290972 [patent_app_country] => US [patent_app_date] => 1981-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2591 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/425/04425700.pdf [firstpage_image] =>[orig_patent_app_number] => 290972 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/290972
Semiconductor device and method for manufacturing the same Aug 6, 1981 Issued
Array ( [id] => 2100537 [patent_doc_number] => 04466172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-21 [patent_title] => 'Method for fabricating MOS device with self-aligned contacts' [patent_app_type] => 1 [patent_app_number] => 6/287388 [patent_app_country] => US [patent_app_date] => 1981-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 31 [patent_no_of_words] => 5310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/466/04466172.pdf [firstpage_image] =>[orig_patent_app_number] => 287388 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/287388
Method for fabricating MOS device with self-aligned contacts Jul 26, 1981 Issued
Array ( [id] => 2114984 [patent_doc_number] => 04476623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-16 [patent_title] => 'Method of fabricating a bipolar dynamic memory cell' [patent_app_type] => 1 [patent_app_number] => 6/279377 [patent_app_country] => US [patent_app_date] => 1981-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3239 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/476/04476623.pdf [firstpage_image] =>[orig_patent_app_number] => 279377 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/279377
Method of fabricating a bipolar dynamic memory cell Jun 30, 1981 Issued
Array ( [id] => 2185050 [patent_doc_number] => 04494300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-22 [patent_title] => 'Process for forming transistors using silicon ribbons as substrates' [patent_app_type] => 1 [patent_app_number] => 6/280148 [patent_app_country] => US [patent_app_date] => 1981-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1946 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/494/04494300.pdf [firstpage_image] =>[orig_patent_app_number] => 280148 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/280148
Process for forming transistors using silicon ribbons as substrates Jun 29, 1981 Issued
Array ( [id] => 2100612 [patent_doc_number] => 04466180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-21 [patent_title] => 'Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping' [patent_app_type] => 1 [patent_app_number] => 6/277464 [patent_app_country] => US [patent_app_date] => 1981-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1375 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/466/04466180.pdf [firstpage_image] =>[orig_patent_app_number] => 277464 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/277464
Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping Jun 24, 1981 Issued
Array ( [id] => 2003914 [patent_doc_number] => 04407694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-10-04 [patent_title] => 'Multi-range doping of epitaxial III-V layers from a single source' [patent_app_type] => 1 [patent_app_number] => 6/276104 [patent_app_country] => US [patent_app_date] => 1981-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3908 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/407/04407694.pdf [firstpage_image] =>[orig_patent_app_number] => 276104 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/276104
Multi-range doping of epitaxial III-V layers from a single source Jun 21, 1981 Issued
Array ( [id] => 2078480 [patent_doc_number] => 04447276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-08 [patent_title] => 'Molecular beam epitaxy electrolytic dopant source' [patent_app_type] => 1 [patent_app_number] => 6/274286 [patent_app_country] => US [patent_app_date] => 1981-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3092 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/447/04447276.pdf [firstpage_image] =>[orig_patent_app_number] => 274286 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/274286
Molecular beam epitaxy electrolytic dopant source Jun 14, 1981 Issued
Array ( [id] => 2011393 [patent_doc_number] => 04418468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-12-06 [patent_title] => 'Process for fabricating a logic structure utilizing polycrystalline silicon Schottky diodes' [patent_app_type] => 1 [patent_app_number] => 6/261842 [patent_app_country] => US [patent_app_date] => 1981-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2606 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/418/04418468.pdf [firstpage_image] =>[orig_patent_app_number] => 261842 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/261842
Process for fabricating a logic structure utilizing polycrystalline silicon Schottky diodes May 7, 1981 Issued
Array ( [id] => 2100528 [patent_doc_number] => 04466171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-21 [patent_title] => 'Method of manufacturing a semiconductor device utilizing outdiffusion to convert an epitaxial layer' [patent_app_type] => 1 [patent_app_number] => 6/257672 [patent_app_country] => US [patent_app_date] => 1981-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 4257 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/466/04466171.pdf [firstpage_image] =>[orig_patent_app_number] => 257672 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/257672
Method of manufacturing a semiconductor device utilizing outdiffusion to convert an epitaxial layer Apr 23, 1981 Issued
06/253441 UTILIZING POLYSILICON DIFFUSION SOURCES AND SPECIAL MASKING TECHNIQUES Apr 12, 1981 Abandoned
Array ( [id] => 2418930 [patent_doc_number] => 04727047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-23 [patent_title] => 'Method of producing sheets of crystalline material' [patent_app_type] => 1 [patent_app_number] => 6/251214 [patent_app_country] => US [patent_app_date] => 1981-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 115 [patent_no_of_words] => 14448 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/727/04727047.pdf [firstpage_image] =>[orig_patent_app_number] => 251214 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/251214
Method of producing sheets of crystalline material Apr 5, 1981 Issued
06/246344 CCD READ ONLY MEMORY Mar 22, 1981 Abandoned
Array ( [id] => 2105924 [patent_doc_number] => 04442449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-04-10 [patent_title] => 'Binary germanium-silicon interconnect and electrode structure for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 6/243986 [patent_app_country] => US [patent_app_date] => 1981-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1062 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/442/04442449.pdf [firstpage_image] =>[orig_patent_app_number] => 243986 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/243986
Binary germanium-silicon interconnect and electrode structure for integrated circuits Mar 15, 1981 Issued
Array ( [id] => 2086315 [patent_doc_number] => 04455737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-06-26 [patent_title] => 'Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines' [patent_app_type] => 1 [patent_app_number] => 6/242442 [patent_app_country] => US [patent_app_date] => 1981-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 38 [patent_no_of_words] => 9057 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/455/04455737.pdf [firstpage_image] =>[orig_patent_app_number] => 242442 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/242442
Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines Mar 10, 1981 Issued
Array ( [id] => 2031018 [patent_doc_number] => 04422888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-12-27 [patent_title] => 'Method for successfully depositing doped II-VI epitaxial layers by organometallic chemical vapor deposition' [patent_app_type] => 1 [patent_app_number] => 6/239080 [patent_app_country] => US [patent_app_date] => 1981-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5844 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/422/04422888.pdf [firstpage_image] =>[orig_patent_app_number] => 239080 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/239080
Method for successfully depositing doped II-VI epitaxial layers by organometallic chemical vapor deposition Feb 26, 1981 Issued
Array ( [id] => 2084073 [patent_doc_number] => 04435224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-06 [patent_title] => 'Process for preparing homogeneous layers of composition Hg.sub.1-x Cd.sub.x' [patent_app_type] => 1 [patent_app_number] => 6/234753 [patent_app_country] => US [patent_app_date] => 1981-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2567 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/435/04435224.pdf [firstpage_image] =>[orig_patent_app_number] => 234753 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/234753
Process for preparing homogeneous layers of composition Hg.sub.1-x Cd.sub.x Feb 16, 1981 Issued
Array ( [id] => 1955395 [patent_doc_number] => 04333227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-06-08 [patent_title] => 'Process for fabricating a self-aligned micrometer bipolar transistor device' [patent_app_type] => 1 [patent_app_number] => 6/224705 [patent_app_country] => US [patent_app_date] => 1981-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5413 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 728 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/333/04333227.pdf [firstpage_image] =>[orig_patent_app_number] => 224705 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/224705
Process for fabricating a self-aligned micrometer bipolar transistor device Jan 11, 1981 Issued
Array ( [id] => 2001328 [patent_doc_number] => 04398338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-08-16 [patent_title] => 'Fabrication of high speed, nonvolatile, electrically erasable memory cell and system utilizing selective masking, deposition and etching techniques' [patent_app_type] => 1 [patent_app_number] => 6/219784 [patent_app_country] => US [patent_app_date] => 1980-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4319 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/398/04398338.pdf [firstpage_image] =>[orig_patent_app_number] => 219784 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/219784
Fabrication of high speed, nonvolatile, electrically erasable memory cell and system utilizing selective masking, deposition and etching techniques Dec 23, 1980 Issued
Array ( [id] => 2025744 [patent_doc_number] => 04378259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-03-29 [patent_title] => 'Method for producing mixed crystal wafer using special temperature control for preliminary gradient and constant layer deposition suitable for fabricating light-emitting diode' [patent_app_type] => 1 [patent_app_number] => 6/219722 [patent_app_country] => US [patent_app_date] => 1980-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3836 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/378/04378259.pdf [firstpage_image] =>[orig_patent_app_number] => 219722 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/219722
Method for producing mixed crystal wafer using special temperature control for preliminary gradient and constant layer deposition suitable for fabricating light-emitting diode Dec 23, 1980 Issued
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