Caroline Koestner

Array ( [id] => 1972481 [patent_doc_number] => 04347656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-07 [patent_title] => 'Method of fabricating polysilicon electrodes' [patent_app_type] => 1 [patent_app_number] => 6/218952 [patent_app_country] => US [patent_app_date] => 1980-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5259 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/347/04347656.pdf [firstpage_image] =>[orig_patent_app_number] => 218952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1995931 [patent_doc_number] => 04383872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-05-17 [patent_title] => 'Method of growing a doped III-V alloy layer by molecular beam epitaxy utilizing a supplemental molecular beam of lead' [patent_app_type] => 1 [patent_app_number] => 6/216339 [patent_app_country] => US [patent_app_date] => 1980-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2957 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/383/04383872.pdf [firstpage_image] =>[orig_patent_app_number] => 216339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1953079 [patent_doc_number] => 04332070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-06-01 [patent_title] => 'Method for forming a headless resistor utilizing selective diffusion and special contact formation' [patent_app_type] => 1 [patent_app_number] => 6/216401 [patent_app_country] => US [patent_app_date] => 1980-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1537 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/332/04332070.pdf [firstpage_image] =>[orig_patent_app_number] => 216401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2038268 [patent_doc_number] => 04404737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-09-20 [patent_title] => 'Method for manufacturing a semiconductor integrated circuit utilizing polycrystalline silicon deposition, oxidation and etching' [patent_app_type] => 1 [patent_app_number] => 6/210759 [patent_app_country] => US [patent_app_date] => 1980-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/404/04404737.pdf [firstpage_image] =>[orig_patent_app_number] => 210759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1960580 [patent_doc_number] => 04349394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-14 [patent_title] => 'Method of making a zener diode utilizing gas-phase epitaxial deposition' [patent_app_type] => 1 [patent_app_number] => 6/206385 [patent_app_country] => US [patent_app_date] => 1980-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2678 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/349/04349394.pdf [firstpage_image] =>[orig_patent_app_number] => 206385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2022518 [patent_doc_number] => 04377899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-03-29 [patent_title] => 'Method of manufacturing Schottky field-effect transistors utilizing shadow masking' [patent_app_type] => 1 [patent_app_number] => 6/206215 [patent_app_country] => US [patent_app_date] => 1980-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 3128 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/377/04377899.pdf [firstpage_image] =>[orig_patent_app_number] => 206215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1959658 [patent_doc_number] => 04358326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-11-09 [patent_title] => 'Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing' [patent_app_type] => 1 [patent_app_number] => 6/203039 [patent_app_country] => US [patent_app_date] => 1980-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2625 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/358/04358326.pdf [firstpage_image] =>[orig_patent_app_number] => 203039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1978652 [patent_doc_number] => 04355457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-26 [patent_title] => 'Method of forming a mesa in a semiconductor device with subsequent separation into individual devices' [patent_app_type] => 1 [patent_app_number] => 6/201826 [patent_app_country] => US [patent_app_date] => 1980-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1761 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/355/04355457.pdf [firstpage_image] =>[orig_patent_app_number] => 201826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2019267 [patent_doc_number] => 04370179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-01-25 [patent_title] => 'Method of making a monolithic complementary Darlington amplifier utilizing diffusion and epitaxial decomposition' [patent_app_type] => 1 [patent_app_number] => 6/200645 [patent_app_country] => US [patent_app_date] => 1980-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 14907 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 503 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/370/04370179.pdf [firstpage_image] =>[orig_patent_app_number] => 200645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1984927 [patent_doc_number] => 04352237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-05 [patent_title] => 'Method for manufacture of integrated semiconductor circuits, in particular CCD-circuits, with self-adjusting, nonoverlapping polysilicon electrodes' [patent_app_type] => 1 [patent_app_number] => 6/187773 [patent_app_country] => US [patent_app_date] => 1980-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2517 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/352/04352237.pdf [firstpage_image] =>[orig_patent_app_number] => 187773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1975627 [patent_doc_number] => 04351100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-28 [patent_title] => 'Method for manufacture of integrated semiconductor circuits, in particular CCD-circuits, with self-adjusting, nonoverlapping polysilicon electrodes' [patent_app_type] => 1 [patent_app_number] => 6/187774 [patent_app_country] => US [patent_app_date] => 1980-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1614 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/351/04351100.pdf [firstpage_image] =>[orig_patent_app_number] => 187774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1948599 [patent_doc_number] => 04354309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-19 [patent_title] => 'Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon' [patent_app_type] => 1 [patent_app_number] => 6/187036 [patent_app_country] => US [patent_app_date] => 1980-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 1845 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354309.pdf [firstpage_image] =>[orig_patent_app_number] => 187036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2022573 [patent_doc_number] => 04377904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-03-29 [patent_title] => 'Method of fabricating a narrow band-gap semiconductor CCD imaging device' [patent_app_type] => 1 [patent_app_number] => 6/185468 [patent_app_country] => US [patent_app_date] => 1980-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1846 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/377/04377904.pdf [firstpage_image] =>[orig_patent_app_number] => 185468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2052275 [patent_doc_number] => RE031506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-24 [patent_title] => 'Method of manufacturing oxide isolated semiconductor device utilizing selective etching technique' [patent_app_type] => 2 [patent_app_number] => 6/183100 [patent_app_country] => US [patent_app_date] => 1980-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 2948 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/031/RE031506.pdf [firstpage_image] =>[orig_patent_app_number] => 183100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2013685 [patent_doc_number] => 04369565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-01-25 [patent_title] => 'Method of manufacturing a semiconductor device utilizing etch and refill to form isolation regions' [patent_app_type] => 1 [patent_app_number] => 6/179983 [patent_app_country] => US [patent_app_date] => 1980-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2709 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/369/04369565.pdf [firstpage_image] =>[orig_patent_app_number] => 179983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1984745 [patent_doc_number] => 04357183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-11-02 [patent_title] => 'Heteroepitaxy of germanium silicon on silicon utilizing alloying control' [patent_app_type] => 1 [patent_app_number] => 6/177567 [patent_app_country] => US [patent_app_date] => 1980-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3019 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/357/04357183.pdf [firstpage_image] =>[orig_patent_app_number] => 177567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1990179 [patent_doc_number] => 04322883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-04-06 [patent_title] => 'Self-aligned metal process for integrated injection logic integrated circuits' [patent_app_type] => 1 [patent_app_number] => 6/167173 [patent_app_country] => US [patent_app_date] => 1980-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4245 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/322/04322883.pdf [firstpage_image] =>[orig_patent_app_number] => 167173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2005423 [patent_doc_number] => 04368085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-01-11 [patent_title] => 'SOS island edge passivation structure' [patent_app_type] => 1 [patent_app_number] => 6/166950 [patent_app_country] => US [patent_app_date] => 1980-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 9 [patent_no_of_words] => 1362 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/368/04368085.pdf [firstpage_image] =>[orig_patent_app_number] => 166950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2043037 [patent_doc_number] => 04378627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-04-05 [patent_title] => 'Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes' [patent_app_type] => 1 [patent_app_number] => 6/167172 [patent_app_country] => US [patent_app_date] => 1980-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 5444 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 468 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/378/04378627.pdf [firstpage_image] =>[orig_patent_app_number] => 167172 [rel_patent_id] =>[rel_patent_doc_number] =>)