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Caroline Koestner

Examiner (ID: 12183)

Most Active Art Unit
1102
Art Unit(s)
1102
Total Applications
74
Issued Applications
68
Pending Applications
0
Abandoned Applications
6

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1972471 [patent_doc_number] => 04347654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-07 [patent_title] => 'Method of fabricating a high-frequency bipolar transistor structure utilizing permeation-etching' [patent_app_type] => 1 [patent_app_number] => 6/160513 [patent_app_country] => US [patent_app_date] => 1980-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3260 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/347/04347654.pdf [firstpage_image] =>[orig_patent_app_number] => 160513 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/160513
Method of fabricating a high-frequency bipolar transistor structure utilizing permeation-etching Jun 17, 1980 Issued
Array ( [id] => 1989081 [patent_doc_number] => 04317276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-03-02 [patent_title] => 'Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer' [patent_app_type] => 1 [patent_app_number] => 6/158680 [patent_app_country] => US [patent_app_date] => 1980-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1509 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/317/04317276.pdf [firstpage_image] =>[orig_patent_app_number] => 158680 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/158680
Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer Jun 11, 1980 Issued
Array ( [id] => 1981993 [patent_doc_number] => 04356622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-11-02 [patent_title] => 'Method of producing low-resistance diffused regions in IC MOS semiconductor circuits in silicon-gate technology metal silicide layer formation' [patent_app_type] => 1 [patent_app_number] => 6/157495 [patent_app_country] => US [patent_app_date] => 1980-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1777 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/356/04356622.pdf [firstpage_image] =>[orig_patent_app_number] => 157495 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/157495
Method of producing low-resistance diffused regions in IC MOS semiconductor circuits in silicon-gate technology metal silicide layer formation Jun 8, 1980 Issued
Array ( [id] => 1957548 [patent_doc_number] => 04348803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-14 [patent_title] => 'Process for producing a semiconductor device having an identification mark in an insulating substrate' [patent_app_type] => 1 [patent_app_number] => 6/156372 [patent_app_country] => US [patent_app_date] => 1980-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2551 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/348/04348803.pdf [firstpage_image] =>[orig_patent_app_number] => 156372 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/156372
Process for producing a semiconductor device having an identification mark in an insulating substrate Jun 3, 1980 Issued
Array ( [id] => 2046875 [patent_doc_number] => 04393572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-07-19 [patent_title] => 'Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques' [patent_app_type] => 1 [patent_app_number] => 6/154601 [patent_app_country] => US [patent_app_date] => 1980-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1767 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/393/04393572.pdf [firstpage_image] =>[orig_patent_app_number] => 154601 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/154601
Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques May 28, 1980 Issued
Array ( [id] => 1929212 [patent_doc_number] => 04346513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-08-31 [patent_title] => 'Method of fabricating semiconductor integrated circuit device utilizing selective etching and epitaxial refill' [patent_app_type] => 1 [patent_app_number] => 6/152024 [patent_app_country] => US [patent_app_date] => 1980-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/346/04346513.pdf [firstpage_image] =>[orig_patent_app_number] => 152024 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/152024
Method of fabricating semiconductor integrated circuit device utilizing selective etching and epitaxial refill May 20, 1980 Issued
Array ( [id] => 1964857 [patent_doc_number] => 04330932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-05-25 [patent_title] => 'Process for preparing isolated junctions in thin-film semiconductors utilizing shadow masked deposition to form graded-side mesas' [patent_app_type] => 1 [patent_app_number] => 6/149801 [patent_app_country] => US [patent_app_date] => 1980-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4403 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/330/04330932.pdf [firstpage_image] =>[orig_patent_app_number] => 149801 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/149801
Process for preparing isolated junctions in thin-film semiconductors utilizing shadow masked deposition to form graded-side mesas May 13, 1980 Issued
Array ( [id] => 1975619 [patent_doc_number] => 04351099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-28 [patent_title] => 'Method of making FET utilizing shadow masking and diffusion from a doped oxide' [patent_app_type] => 1 [patent_app_number] => 6/149621 [patent_app_country] => US [patent_app_date] => 1980-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4025 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/351/04351099.pdf [firstpage_image] =>[orig_patent_app_number] => 149621 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/149621
Method of making FET utilizing shadow masking and diffusion from a doped oxide May 11, 1980 Issued
Array ( [id] => 1883436 [patent_doc_number] => 04295898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-10-20 [patent_title] => 'Method of making isolated semiconductor devices utilizing ion-implantation of aluminum and heat treating' [patent_app_type] => 1 [patent_app_number] => 6/147715 [patent_app_country] => US [patent_app_date] => 1980-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2429 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/295/04295898.pdf [firstpage_image] =>[orig_patent_app_number] => 147715 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/147715
Method of making isolated semiconductor devices utilizing ion-implantation of aluminum and heat treating May 7, 1980 Issued
Array ( [id] => 1995414 [patent_doc_number] => 04379726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-04-12 [patent_title] => 'Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition' [patent_app_type] => 1 [patent_app_number] => 6/147334 [patent_app_country] => US [patent_app_date] => 1980-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2017 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/379/04379726.pdf [firstpage_image] =>[orig_patent_app_number] => 147334 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/147334
Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition May 5, 1980 Issued
Array ( [id] => 1988167 [patent_doc_number] => 04328611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-05-11 [patent_title] => 'Method for manufacture of an interdigitated collector structure utilizing etch and refill techniques' [patent_app_type] => 1 [patent_app_number] => 6/144672 [patent_app_country] => US [patent_app_date] => 1980-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2270 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/328/04328611.pdf [firstpage_image] =>[orig_patent_app_number] => 144672 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/144672
Method for manufacture of an interdigitated collector structure utilizing etch and refill techniques Apr 27, 1980 Issued
Array ( [id] => 1894559 [patent_doc_number] => 04282045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-08-04 [patent_title] => 'Pb.sub.1-W Cd.sub.W S Epitaxial thin film' [patent_app_type] => 1 [patent_app_number] => 6/143562 [patent_app_country] => US [patent_app_date] => 1980-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7364 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/282/04282045.pdf [firstpage_image] =>[orig_patent_app_number] => 143562 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/143562
Pb.sub.1-W Cd.sub.W S Epitaxial thin film Apr 24, 1980 Issued
Array ( [id] => 1962061 [patent_doc_number] => 04349691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-14 [patent_title] => 'Method of making constant voltage solar cell and product formed thereby utilizing low-temperature aluminum diffusion' [patent_app_type] => 1 [patent_app_number] => 6/143780 [patent_app_country] => US [patent_app_date] => 1980-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1490 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/349/04349691.pdf [firstpage_image] =>[orig_patent_app_number] => 143780 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/143780
Method of making constant voltage solar cell and product formed thereby utilizing low-temperature aluminum diffusion Apr 24, 1980 Issued
Array ( [id] => 1952411 [patent_doc_number] => 04316319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-02-23 [patent_title] => 'Method for making a high sheet resistance structure for high density integrated circuits' [patent_app_type] => 1 [patent_app_number] => 6/141717 [patent_app_country] => US [patent_app_date] => 1980-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3975 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/316/04316319.pdf [firstpage_image] =>[orig_patent_app_number] => 141717 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/141717
Method for making a high sheet resistance structure for high density integrated circuits Apr 17, 1980 Issued
Array ( [id] => 1944138 [patent_doc_number] => 04341010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-07-27 [patent_title] => 'Fabrication of electroluminescent semiconductor device utilizing selective etching and epitaxial deposition' [patent_app_type] => 1 [patent_app_number] => 6/141511 [patent_app_country] => US [patent_app_date] => 1980-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1965 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/341/04341010.pdf [firstpage_image] =>[orig_patent_app_number] => 141511 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/141511
Fabrication of electroluminescent semiconductor device utilizing selective etching and epitaxial deposition Apr 17, 1980 Issued
Array ( [id] => 1984932 [patent_doc_number] => 04352238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-05 [patent_title] => 'Process for fabricating a vertical static induction device' [patent_app_type] => 1 [patent_app_number] => 6/139754 [patent_app_country] => US [patent_app_date] => 1980-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 18 [patent_no_of_words] => 2978 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/352/04352238.pdf [firstpage_image] =>[orig_patent_app_number] => 139754 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/139754
Process for fabricating a vertical static induction device Apr 13, 1980 Issued
Array ( [id] => 1873521 [patent_doc_number] => 04304043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-12-08 [patent_title] => 'Process for preparing semiconductor device _by forming reinforcing regions to facilitate separation of pellets' [patent_app_type] => 1 [patent_app_number] => 6/137971 [patent_app_country] => US [patent_app_date] => 1980-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4518 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/304/04304043.pdf [firstpage_image] =>[orig_patent_app_number] => 137971 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/137971
Process for preparing semiconductor device _by forming reinforcing regions to facilitate separation of pellets Apr 6, 1980 Issued
Array ( [id] => 1961562 [patent_doc_number] => 04329772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-05-18 [patent_title] => 'Method for manufacturing a semiconductor device utilizing selective epitaxial growth and post heat treating' [patent_app_type] => 1 [patent_app_number] => 6/134673 [patent_app_country] => US [patent_app_date] => 1980-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 3138 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/329/04329772.pdf [firstpage_image] =>[orig_patent_app_number] => 134673 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/134673
Method for manufacturing a semiconductor device utilizing selective epitaxial growth and post heat treating Mar 26, 1980 Issued
Array ( [id] => 1992602 [patent_doc_number] => 04344803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-08-17 [patent_title] => 'Photo cathode made from composite semiconductor/glass material' [patent_app_type] => 1 [patent_app_number] => 6/130124 [patent_app_country] => US [patent_app_date] => 1980-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1024 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/344/04344803.pdf [firstpage_image] =>[orig_patent_app_number] => 130124 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/130124
Photo cathode made from composite semiconductor/glass material Mar 12, 1980 Issued
Array ( [id] => 1968747 [patent_doc_number] => 04318751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-03-09 [patent_title] => 'Self-aligned process for providing an improved high performance bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 6/129928 [patent_app_country] => US [patent_app_date] => 1980-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3549 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/318/04318751.pdf [firstpage_image] =>[orig_patent_app_number] => 129928 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/129928
Self-aligned process for providing an improved high performance bipolar transistor Mar 12, 1980 Issued
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