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Caroline Koestner

Examiner (ID: 12183)

Most Active Art Unit
1102
Art Unit(s)
1102
Total Applications
74
Issued Applications
68
Pending Applications
0
Abandoned Applications
6

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1894998 [patent_doc_number] => 04292730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-10-06 [patent_title] => 'Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization' [patent_app_type] => 1 [patent_app_number] => 6/129913 [patent_app_country] => US [patent_app_date] => 1980-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 2978 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/292/04292730.pdf [firstpage_image] =>[orig_patent_app_number] => 129913 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/129913
Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization Mar 11, 1980 Issued
Array ( [id] => 1948833 [patent_doc_number] => 04309812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-01-12 [patent_title] => 'Process for fabricating improved bipolar transistor utilizing selective etching' [patent_app_type] => 1 [patent_app_number] => 6/126610 [patent_app_country] => US [patent_app_date] => 1980-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 4286 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/309/04309812.pdf [firstpage_image] =>[orig_patent_app_number] => 126610 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/126610
Process for fabricating improved bipolar transistor utilizing selective etching Mar 2, 1980 Issued
Array ( [id] => 1897552 [patent_doc_number] => 04263067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-04-21 [patent_title] => 'Fabrication of transistors having specifically paired dopants' [patent_app_type] => 1 [patent_app_number] => 6/123276 [patent_app_country] => US [patent_app_date] => 1980-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3239 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/263/04263067.pdf [firstpage_image] =>[orig_patent_app_number] => 123276 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/123276
Fabrication of transistors having specifically paired dopants Feb 20, 1980 Issued
Array ( [id] => 1891108 [patent_doc_number] => 04260436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-04-07 [patent_title] => 'Fabrication of moat resistor ram cell utilizing polycrystalline deposition and etching' [patent_app_type] => 1 [patent_app_number] => 6/122778 [patent_app_country] => US [patent_app_date] => 1980-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2180 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/260/04260436.pdf [firstpage_image] =>[orig_patent_app_number] => 122778 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/122778
Fabrication of moat resistor ram cell utilizing polycrystalline deposition and etching Feb 18, 1980 Issued
Array ( [id] => 1964254 [patent_doc_number] => 04315056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-02-09 [patent_title] => 'Low tin terne coated steel article' [patent_app_type] => 1 [patent_app_number] => 6/118073 [patent_app_country] => US [patent_app_date] => 1980-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1546 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/315/04315056.pdf [firstpage_image] =>[orig_patent_app_number] => 118073 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/118073
Low tin terne coated steel article Feb 3, 1980 Issued
Array ( [id] => 1923887 [patent_doc_number] => 04298402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-11-03 [patent_title] => 'Method of fabricating self-aligned lateral bipolar transistor utilizing special masking techniques' [patent_app_type] => 1 [patent_app_number] => 6/118291 [patent_app_country] => US [patent_app_date] => 1980-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1566 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/298/04298402.pdf [firstpage_image] =>[orig_patent_app_number] => 118291 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/118291
Method of fabricating self-aligned lateral bipolar transistor utilizing special masking techniques Feb 3, 1980 Issued
Array ( [id] => 1914732 [patent_doc_number] => 04290188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-09-22 [patent_title] => 'Process for producing bipolar semiconductor device utilizing predeposition of dopant and a polycrystalline silicon-gold film followed by simultaneous diffusion' [patent_app_type] => 1 [patent_app_number] => 6/116974 [patent_app_country] => US [patent_app_date] => 1980-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1963 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/290/04290188.pdf [firstpage_image] =>[orig_patent_app_number] => 116974 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/116974
Process for producing bipolar semiconductor device utilizing predeposition of dopant and a polycrystalline silicon-gold film followed by simultaneous diffusion Jan 29, 1980 Issued
Array ( [id] => 2120041 [patent_doc_number] => 04430793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-14 [patent_title] => 'Method of manufacturing a semiconductor device utilizing selective introduction of a dopant thru a deposited semiconductor contact layer' [patent_app_type] => 1 [patent_app_number] => 6/111401 [patent_app_country] => US [patent_app_date] => 1980-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5776 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/430/04430793.pdf [firstpage_image] =>[orig_patent_app_number] => 111401 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/111401
Method of manufacturing a semiconductor device utilizing selective introduction of a dopant thru a deposited semiconductor contact layer Jan 10, 1980 Issued
Array ( [id] => 1864319 [patent_doc_number] => 04268584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-05-19 [patent_title] => 'Nickel-X/gold/nickel-X conductors for solid state devices where X is phosphorus, boron, or carbon' [patent_app_type] => 1 [patent_app_number] => 6/103969 [patent_app_country] => US [patent_app_date] => 1979-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3963 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/268/04268584.pdf [firstpage_image] =>[orig_patent_app_number] => 103969 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/103969
Nickel-X/gold/nickel-X conductors for solid state devices where X is phosphorus, boron, or carbon Dec 16, 1979 Issued
Array ( [id] => 1897156 [patent_doc_number] => 04265685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-05-05 [patent_title] => 'Utilizing simultaneous masking and diffusion of peripheral substrate areas' [patent_app_type] => 1 [patent_app_number] => 6/098140 [patent_app_country] => US [patent_app_date] => 1979-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2026 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/265/04265685.pdf [firstpage_image] =>[orig_patent_app_number] => 098140 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/098140
Utilizing simultaneous masking and diffusion of peripheral substrate areas Nov 27, 1979 Issued
Array ( [id] => 1888256 [patent_doc_number] => 04280858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-28 [patent_title] => 'Method of manufacturing a semiconductor device by retarding the diffusion of zinc or cadmium into a device region' [patent_app_type] => 1 [patent_app_number] => 6/091428 [patent_app_country] => US [patent_app_date] => 1979-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2113 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/280/04280858.pdf [firstpage_image] =>[orig_patent_app_number] => 091428 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/091428
Method of manufacturing a semiconductor device by retarding the diffusion of zinc or cadmium into a device region Nov 4, 1979 Issued
Array ( [id] => 1930673 [patent_doc_number] => 04261771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-04-14 [patent_title] => 'Method of fabricating periodic monolayer semiconductor structures by molecular beam epitaxy' [patent_app_type] => 1 [patent_app_number] => 6/090020 [patent_app_country] => US [patent_app_date] => 1979-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 7143 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/261/04261771.pdf [firstpage_image] =>[orig_patent_app_number] => 090020 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/090020
Method of fabricating periodic monolayer semiconductor structures by molecular beam epitaxy Oct 30, 1979 Issued
Array ( [id] => 1885346 [patent_doc_number] => 04280271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-28 [patent_title] => 'Three level interconnect process for manufacture of integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 6/083702 [patent_app_country] => US [patent_app_date] => 1979-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2334 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/280/04280271.pdf [firstpage_image] =>[orig_patent_app_number] => 083702 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/083702
Three level interconnect process for manufacture of integrated circuit devices Oct 10, 1979 Issued
Array ( [id] => 1883358 [patent_doc_number] => 04273594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-16 [patent_title] => 'Gallium arsenide devices having reduced surface recombination velocity' [patent_app_type] => 1 [patent_app_number] => 6/082002 [patent_app_country] => US [patent_app_date] => 1979-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2512 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/273/04273594.pdf [firstpage_image] =>[orig_patent_app_number] => 082002 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/082002
Gallium arsenide devices having reduced surface recombination velocity Oct 4, 1979 Issued
Array ( [id] => 1912291 [patent_doc_number] => 04270960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-02 [patent_title] => 'Method of manufacturing a semiconductor device utilizing a mono-polycrystalline deposition on a predeposited amorphous layer' [patent_app_type] => 1 [patent_app_number] => 6/081754 [patent_app_country] => US [patent_app_date] => 1979-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1388 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/270/04270960.pdf [firstpage_image] =>[orig_patent_app_number] => 081754 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/081754
Method of manufacturing a semiconductor device utilizing a mono-polycrystalline deposition on a predeposited amorphous layer Oct 2, 1979 Issued
Array ( [id] => 1918658 [patent_doc_number] => 04264381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-04-28 [patent_title] => 'Fabrication of injection lasers utilizing a porous host diffusion layer' [patent_app_type] => 1 [patent_app_number] => 6/080355 [patent_app_country] => US [patent_app_date] => 1979-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 16 [patent_no_of_words] => 5464 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/264/04264381.pdf [firstpage_image] =>[orig_patent_app_number] => 080355 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/080355
Fabrication of injection lasers utilizing a porous host diffusion layer Sep 27, 1979 Issued
Array ( [id] => 1869709 [patent_doc_number] => 04283236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-08-11 [patent_title] => 'Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping' [patent_app_type] => 1 [patent_app_number] => 6/077234 [patent_app_country] => US [patent_app_date] => 1979-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2214 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/283/04283236.pdf [firstpage_image] =>[orig_patent_app_number] => 077234 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/077234
Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping Sep 18, 1979 Issued
Array ( [id] => 3379838 [patent_doc_number] => 04242133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1980-12-30 [patent_title] => 'Copper base alloy containing manganese' [patent_app_type] => 1 [patent_app_number] => 6/074536 [patent_app_country] => US [patent_app_date] => 1979-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2271 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/242/04242133.pdf [firstpage_image] =>[orig_patent_app_number] => 074536 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/074536
Copper base alloy containing manganese Sep 10, 1979 Issued
Array ( [id] => 2043067 [patent_doc_number] => 04378629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-04-05 [patent_title] => 'Semiconductor embedded layer technology including permeable base transistor, fabrication method' [patent_app_type] => 1 [patent_app_number] => 6/065514 [patent_app_country] => US [patent_app_date] => 1979-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 94 [patent_no_of_words] => 16104 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/378/04378629.pdf [firstpage_image] =>[orig_patent_app_number] => 065514 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/065514
Semiconductor embedded layer technology including permeable base transistor, fabrication method Aug 9, 1979 Issued
Array ( [id] => 1875666 [patent_doc_number] => 04279670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-21 [patent_title] => 'Semiconductor device manufacturing methods utilizing a predetermined flow of reactive substance over a dopant material' [patent_app_type] => 1 [patent_app_number] => 6/064339 [patent_app_country] => US [patent_app_date] => 1979-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8145 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/279/04279670.pdf [firstpage_image] =>[orig_patent_app_number] => 064339 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/064339
Semiconductor device manufacturing methods utilizing a predetermined flow of reactive substance over a dopant material Aug 5, 1979 Issued
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