Caroline Koestner
Examiner (ID: 12183)
Most Active Art Unit | 1102 |
Art Unit(s) | 1102 |
Total Applications | 74 |
Issued Applications | 68 |
Pending Applications | 0 |
Abandoned Applications | 6 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2091655
[patent_doc_number] => 04468852
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-09-04
[patent_title] => 'Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation'
[patent_app_type] => 1
[patent_app_number] => 6/482156
[patent_app_country] => US
[patent_app_date] => 1983-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3649
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 475
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/468/04468852.pdf
[firstpage_image] =>[orig_patent_app_number] => 482156
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/482156 | Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation | Apr 4, 1983 | Issued |
Array
(
[id] => 2199175
[patent_doc_number] => 04523964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-06-18
[patent_title] => 'High temperature layered silicon structures'
[patent_app_type] => 1
[patent_app_number] => 6/480528
[patent_app_country] => US
[patent_app_date] => 1983-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 3071
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/523/04523964.pdf
[firstpage_image] =>[orig_patent_app_number] => 480528
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/480528 | High temperature layered silicon structures | Mar 29, 1983 | Issued |
Array
(
[id] => 2056959
[patent_doc_number] => 04486942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-12-11
[patent_title] => 'Method of manufacturing semiconductor integrated circuit BI-MOS device'
[patent_app_type] => 1
[patent_app_number] => 6/478590
[patent_app_country] => US
[patent_app_date] => 1983-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 2414
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/486/04486942.pdf
[firstpage_image] =>[orig_patent_app_number] => 478590
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/478590 | Method of manufacturing semiconductor integrated circuit BI-MOS device | Mar 23, 1983 | Issued |
Array
(
[id] => 2251371
[patent_doc_number] => 04569120
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-11
[patent_title] => 'Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation'
[patent_app_type] => 1
[patent_app_number] => 6/472803
[patent_app_country] => US
[patent_app_date] => 1983-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 4089
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/569/04569120.pdf
[firstpage_image] =>[orig_patent_app_number] => 472803
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/472803 | Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation | Mar 6, 1983 | Issued |
Array
(
[id] => 2251382
[patent_doc_number] => 04569121
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-11
[patent_title] => 'Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer'
[patent_app_type] => 1
[patent_app_number] => 6/472804
[patent_app_country] => US
[patent_app_date] => 1983-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3755
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/569/04569121.pdf
[firstpage_image] =>[orig_patent_app_number] => 472804
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/472804 | Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer | Mar 6, 1983 | Issued |
Array
(
[id] => 2214490
[patent_doc_number] => 04570328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-18
[patent_title] => 'Method of producing titanium nitride MOS device gate electrode'
[patent_app_type] => 1
[patent_app_number] => 6/472517
[patent_app_country] => US
[patent_app_date] => 1983-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2388
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/570/04570328.pdf
[firstpage_image] =>[orig_patent_app_number] => 472517
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/472517 | Method of producing titanium nitride MOS device gate electrode | Mar 6, 1983 | Issued |
Array
(
[id] => 2117386
[patent_doc_number] => 04481707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-11-13
[patent_title] => 'Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor'
[patent_app_type] => 1
[patent_app_number] => 6/469370
[patent_app_country] => US
[patent_app_date] => 1983-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1309
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/481/04481707.pdf
[firstpage_image] =>[orig_patent_app_number] => 469370
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/469370 | Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor | Feb 23, 1983 | Issued |
Array
(
[id] => 2063849
[patent_doc_number] => 04487640
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-12-11
[patent_title] => 'Method for the preparation of epitaxial films of mercury cadmium telluride'
[patent_app_type] => 1
[patent_app_number] => 6/468781
[patent_app_country] => US
[patent_app_date] => 1983-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2961
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/487/04487640.pdf
[firstpage_image] =>[orig_patent_app_number] => 468781
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/468781 | Method for the preparation of epitaxial films of mercury cadmium telluride | Feb 21, 1983 | Issued |
Array
(
[id] => 2267717
[patent_doc_number] => 04565584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-01-21
[patent_title] => 'Method of producing single crystal film utilizing a two-step heat treatment'
[patent_app_type] => 1
[patent_app_number] => 6/460801
[patent_app_country] => US
[patent_app_date] => 1983-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3519
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/565/04565584.pdf
[firstpage_image] =>[orig_patent_app_number] => 460801
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/460801 | Method of producing single crystal film utilizing a two-step heat treatment | Jan 24, 1983 | Issued |
Array
(
[id] => 2183162
[patent_doc_number] => 04501060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-02-26
[patent_title] => 'Dielectrically isolated semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 6/460399
[patent_app_country] => US
[patent_app_date] => 1983-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5527
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/501/04501060.pdf
[firstpage_image] =>[orig_patent_app_number] => 460399
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/460399 | Dielectrically isolated semiconductor devices | Jan 23, 1983 | Issued |
Array
(
[id] => 2194952
[patent_doc_number] => 04495010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-01-22
[patent_title] => 'Method for manufacturing fast bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 6/460504
[patent_app_country] => US
[patent_app_date] => 1983-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3055
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 376
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/495/04495010.pdf
[firstpage_image] =>[orig_patent_app_number] => 460504
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/460504 | Method for manufacturing fast bipolar transistors | Jan 23, 1983 | Issued |
Array
(
[id] => 2175506
[patent_doc_number] => 04545109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-10-08
[patent_title] => 'Method of making a gallium arsenide field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 6/459756
[patent_app_country] => US
[patent_app_date] => 1983-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 12
[patent_no_of_words] => 1796
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/545/04545109.pdf
[firstpage_image] =>[orig_patent_app_number] => 459756
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/459756 | Method of making a gallium arsenide field effect transistor | Jan 20, 1983 | Issued |
Array
(
[id] => 2326718
[patent_doc_number] => 04705759
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-11-10
[patent_title] => 'High power MOSFET with low on-resistance and high breakdown voltage'
[patent_app_type] => 1
[patent_app_number] => 6/456813
[patent_app_country] => US
[patent_app_date] => 1983-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3767
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 440
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/705/04705759.pdf
[firstpage_image] =>[orig_patent_app_number] => 456813
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/456813 | High power MOSFET with low on-resistance and high breakdown voltage | Jan 9, 1983 | Issued |
Array
(
[id] => 2063839
[patent_doc_number] => 04487639
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-12-11
[patent_title] => 'Localized epitaxy for VLSI devices'
[patent_app_type] => 1
[patent_app_number] => 6/456209
[patent_app_country] => US
[patent_app_date] => 1983-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 2165
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/487/04487639.pdf
[firstpage_image] =>[orig_patent_app_number] => 456209
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/456209 | Localized epitaxy for VLSI devices | Jan 6, 1983 | Issued |
Array
(
[id] => 2098156
[patent_doc_number] => 04471522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-09-18
[patent_title] => 'Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes'
[patent_app_type] => 1
[patent_app_number] => 6/455386
[patent_app_country] => US
[patent_app_date] => 1983-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 20
[patent_no_of_words] => 5463
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/471/04471522.pdf
[firstpage_image] =>[orig_patent_app_number] => 455386
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/455386 | Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes | Jan 2, 1983 | Issued |
Array
(
[id] => 2145471
[patent_doc_number] => 04497665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-02-05
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 6/455327
[patent_app_country] => US
[patent_app_date] => 1983-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 14
[patent_no_of_words] => 3560
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/497/04497665.pdf
[firstpage_image] =>[orig_patent_app_number] => 455327
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/455327 | Method for manufacturing semiconductor device | Jan 2, 1983 | Issued |
Array
(
[id] => 2163953
[patent_doc_number] => 04546539
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-10-15
[patent_title] => 'I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 6/447946
[patent_app_country] => US
[patent_app_date] => 1982-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3419
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/546/04546539.pdf
[firstpage_image] =>[orig_patent_app_number] => 447946
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/447946 | I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors | Dec 7, 1982 | Issued |
Array
(
[id] => 2166809
[patent_doc_number] => 04507848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-04-02
[patent_title] => 'Control of substrate injection in lateral bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 6/443846
[patent_app_country] => US
[patent_app_date] => 1982-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 2713
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/507/04507848.pdf
[firstpage_image] =>[orig_patent_app_number] => 443846
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/443846 | Control of substrate injection in lateral bipolar transistors | Nov 21, 1982 | Issued |
Array
(
[id] => 2116424
[patent_doc_number] => 04488914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-12-18
[patent_title] => 'Process for the epitaxial deposition of III-V compounds utilizing a continuous in-situ hydrogen chloride etch'
[patent_app_type] => 1
[patent_app_number] => 6/437655
[patent_app_country] => US
[patent_app_date] => 1982-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 4230
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/488/04488914.pdf
[firstpage_image] =>[orig_patent_app_number] => 437655
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/437655 | Process for the epitaxial deposition of III-V compounds utilizing a continuous in-situ hydrogen chloride etch | Oct 28, 1982 | Issued |
06/431055 | SEMICONDUCTOR EMBEDDED LAYER TECHNOLOGY | Sep 29, 1982 | Abandoned |