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Caroline Koestner

Examiner (ID: 12183)

Most Active Art Unit
1102
Art Unit(s)
1102
Total Applications
74
Issued Applications
68
Pending Applications
0
Abandoned Applications
6

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2050538 [patent_doc_number] => 04408387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-10-11 [patent_title] => 'Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask' [patent_app_type] => 1 [patent_app_number] => 6/425648 [patent_app_country] => US [patent_app_date] => 1982-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2154 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/408/04408387.pdf [firstpage_image] =>[orig_patent_app_number] => 425648 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/425648
Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask Sep 27, 1982 Issued
Array ( [id] => 2088608 [patent_doc_number] => 04473940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-02 [patent_title] => 'Method of producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 6/425651 [patent_app_country] => US [patent_app_date] => 1982-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2972 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/473/04473940.pdf [firstpage_image] =>[orig_patent_app_number] => 425651 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/425651
Method of producing a semiconductor device Sep 27, 1982 Issued
Array ( [id] => 2216633 [patent_doc_number] => 04578127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-25 [patent_title] => 'Method of making an improved group III-V semiconductor device utilizing a getter-smoothing layer' [patent_app_type] => 1 [patent_app_number] => 6/408009 [patent_app_country] => US [patent_app_date] => 1982-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2525 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/578/04578127.pdf [firstpage_image] =>[orig_patent_app_number] => 408009 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/408009
Method of making an improved group III-V semiconductor device utilizing a getter-smoothing layer Aug 12, 1982 Issued
Array ( [id] => 2152382 [patent_doc_number] => 04499657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-02-19 [patent_title] => 'Method of making a semiconductor device having protected edges' [patent_app_type] => 1 [patent_app_number] => 6/404051 [patent_app_country] => US [patent_app_date] => 1982-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 6073 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/499/04499657.pdf [firstpage_image] =>[orig_patent_app_number] => 404051 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/404051
Method of making a semiconductor device having protected edges Aug 1, 1982 Issued
Array ( [id] => 2082992 [patent_doc_number] => 04485552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-04 [patent_title] => 'Complementary transistor structure and method for manufacture' [patent_app_type] => 1 [patent_app_number] => 6/399927 [patent_app_country] => US [patent_app_date] => 1982-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 5729 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/485/04485552.pdf [firstpage_image] =>[orig_patent_app_number] => 399927 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/399927
Complementary transistor structure and method for manufacture Jul 18, 1982 Issued
Array ( [id] => 2062517 [patent_doc_number] => 04477962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-23 [patent_title] => 'Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines' [patent_app_type] => 1 [patent_app_number] => 6/397050 [patent_app_country] => US [patent_app_date] => 1982-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 38 [patent_no_of_words] => 9055 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/477/04477962.pdf [firstpage_image] =>[orig_patent_app_number] => 397050 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/397050
Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines Jul 11, 1982 Issued
Array ( [id] => 2166715 [patent_doc_number] => 04506437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-26 [patent_title] => 'Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines' [patent_app_type] => 1 [patent_app_number] => 6/397052 [patent_app_country] => US [patent_app_date] => 1982-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 38 [patent_no_of_words] => 9057 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/506/04506437.pdf [firstpage_image] =>[orig_patent_app_number] => 397052 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/397052
Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines Jul 11, 1982 Issued
Array ( [id] => 2117378 [patent_doc_number] => 04481706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-13 [patent_title] => 'Process for manufacturing integrated bi-polar transistors of very small dimensions' [patent_app_type] => 1 [patent_app_number] => 6/392366 [patent_app_country] => US [patent_app_date] => 1982-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3510 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/481/04481706.pdf [firstpage_image] =>[orig_patent_app_number] => 392366 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/392366
Process for manufacturing integrated bi-polar transistors of very small dimensions Jun 24, 1982 Issued
Array ( [id] => 2070045 [patent_doc_number] => 04462847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-07-31 [patent_title] => 'Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition' [patent_app_type] => 1 [patent_app_number] => 6/390011 [patent_app_country] => US [patent_app_date] => 1982-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1266 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/462/04462847.pdf [firstpage_image] =>[orig_patent_app_number] => 390011 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/390011
Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition Jun 20, 1982 Issued
06/389777 METHOD OF FABRICATING PATTERNED EXPITAXIAL SILICON FILMS AND DEVICES MADE THEREBY Jun 17, 1982 Abandoned
Array ( [id] => 2108453 [patent_doc_number] => 04479297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-30 [patent_title] => 'Method of fabricating three-dimensional semiconductor devices utilizing CeO.sub.2 and ion-implantation.' [patent_app_type] => 1 [patent_app_number] => 6/386808 [patent_app_country] => US [patent_app_date] => 1982-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 4095 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/479/04479297.pdf [firstpage_image] =>[orig_patent_app_number] => 386808 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/386808
Method of fabricating three-dimensional semiconductor devices utilizing CeO.sub.2 and ion-implantation. Jun 8, 1982 Issued
Array ( [id] => 2169665 [patent_doc_number] => 04503598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-12 [patent_title] => 'Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques' [patent_app_type] => 1 [patent_app_number] => 6/380170 [patent_app_country] => US [patent_app_date] => 1982-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2208 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/503/04503598.pdf [firstpage_image] =>[orig_patent_app_number] => 380170 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/380170
Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques May 19, 1982 Issued
Array ( [id] => 2072704 [patent_doc_number] => 04433470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-28 [patent_title] => 'Method for manufacturing semiconductor device utilizing selective etching and diffusion' [patent_app_type] => 1 [patent_app_number] => 6/378480 [patent_app_country] => US [patent_app_date] => 1982-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 8502 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/433/04433470.pdf [firstpage_image] =>[orig_patent_app_number] => 378480 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/378480
Method for manufacturing semiconductor device utilizing selective etching and diffusion May 13, 1982 Issued
Array ( [id] => 2105900 [patent_doc_number] => 04435895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-13 [patent_title] => 'Process for forming complementary integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 6/365396 [patent_app_country] => US [patent_app_date] => 1982-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4066 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/435/04435895.pdf [firstpage_image] =>[orig_patent_app_number] => 365396 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/365396
Process for forming complementary integrated circuit devices Apr 4, 1982 Issued
Array ( [id] => 2105929 [patent_doc_number] => 04435898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-13 [patent_title] => 'Method for making a base etched transistor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 6/360731 [patent_app_country] => US [patent_app_date] => 1982-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4000 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/435/04435898.pdf [firstpage_image] =>[orig_patent_app_number] => 360731 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/360731
Method for making a base etched transistor integrated circuit Mar 21, 1982 Issued
Array ( [id] => 2098184 [patent_doc_number] => 04471525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-09-18 [patent_title] => 'Method for manufacturing semiconductor device utilizing two-step etch and selective oxidation to form isolation regions' [patent_app_type] => 1 [patent_app_number] => 6/359485 [patent_app_country] => US [patent_app_date] => 1982-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 58 [patent_no_of_words] => 11281 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/471/04471525.pdf [firstpage_image] =>[orig_patent_app_number] => 359485 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/359485
Method for manufacturing semiconductor device utilizing two-step etch and selective oxidation to form isolation regions Mar 17, 1982 Issued
Array ( [id] => 2034450 [patent_doc_number] => 04412376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-01 [patent_title] => 'Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation' [patent_app_type] => 1 [patent_app_number] => 6/355059 [patent_app_country] => US [patent_app_date] => 1982-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3425 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/412/04412376.pdf [firstpage_image] =>[orig_patent_app_number] => 355059 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/355059
Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation Mar 4, 1982 Issued
Array ( [id] => 2034469 [patent_doc_number] => 04412378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-01 [patent_title] => 'Method for manufacturing semiconductor device utilizing selective masking, etching and oxidation' [patent_app_type] => 1 [patent_app_number] => 6/351251 [patent_app_country] => US [patent_app_date] => 1982-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3255 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/412/04412378.pdf [firstpage_image] =>[orig_patent_app_number] => 351251 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/351251
Method for manufacturing semiconductor device utilizing selective masking, etching and oxidation Feb 21, 1982 Issued
06/349229 HIGH DENSITY VMOS ELECTRICALLY PROGRAMMABLE ROM Feb 15, 1982 Abandoned
Array ( [id] => 2094245 [patent_doc_number] => 04445268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-01 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit BI-MOS device' [patent_app_type] => 1 [patent_app_number] => 6/348541 [patent_app_country] => US [patent_app_date] => 1982-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2418 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/445/04445268.pdf [firstpage_image] =>[orig_patent_app_number] => 348541 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/348541
Method of manufacturing a semiconductor integrated circuit BI-MOS device Feb 11, 1982 Issued
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