
Cassandra F. Cox
Examiner (ID: 13913, Phone: (571)272-1741 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2842, 2816, 2849, 2836 |
| Total Applications | 2134 |
| Issued Applications | 1986 |
| Pending Applications | 78 |
| Abandoned Applications | 84 |
Applications
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|---|---|---|---|
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