Search

Cassandra F. Cox

Examiner (ID: 13913, Phone: (571)272-1741 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2842, 2816, 2849, 2836
Total Applications
2134
Issued Applications
1986
Pending Applications
78
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19080616 [patent_doc_number] => 11950004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Counting method, a counting device and a counting system and a pixel array using the counting device [patent_app_type] => utility [patent_app_number] => 17/239594 [patent_app_country] => US [patent_app_date] => 2021-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239594
Counting method, a counting device and a counting system and a pixel array using the counting device Apr 23, 2021 Issued
Array ( [id] => 18336669 [patent_doc_number] => 20230128618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => TIME MEASUREMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/919153 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17919153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/919153
Time measurement system Apr 14, 2021 Issued
Array ( [id] => 17709743 [patent_doc_number] => 20220209751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DUTY CYCLE DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/229348 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229348
Duty cycle detection circuit and duty cycle correction circuit including the same Apr 12, 2021 Issued
Array ( [id] => 17934114 [patent_doc_number] => 20220329240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => POWER SWITCH DEVICE DRIVER WITH ENERGY RECOVERING AND THE METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/229463 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229463
Power switch device driver with energy recovering and the method thereof Apr 12, 2021 Issued
Array ( [id] => 18984213 [patent_doc_number] => 11909408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => SerDes module clock network architecture [patent_app_type] => utility [patent_app_number] => 17/907099 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1443 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17907099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/907099
SerDes module clock network architecture Mar 23, 2021 Issued
Array ( [id] => 17717229 [patent_doc_number] => 11381232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Duty cycle correction method and circuit thereof [patent_app_type] => utility [patent_app_number] => 17/196478 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196478
Duty cycle correction method and circuit thereof Mar 8, 2021 Issued
Array ( [id] => 17364721 [patent_doc_number] => 11231742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-25 [patent_title] => Clock distribution resonator system [patent_app_type] => utility [patent_app_number] => 17/194462 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194462
Clock distribution resonator system Mar 7, 2021 Issued
Array ( [id] => 17086247 [patent_doc_number] => 20210281254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => PROGRAMMABLE-ON-THE-FLY FRACTIONAL DIVIDER IN ACCORDANCE WITH THIS DISCLOSURE [patent_app_type] => utility [patent_app_number] => 17/193532 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193532
Programmable-on-the-fly fractional divider in accordance with this disclosure Mar 4, 2021 Issued
Array ( [id] => 17853507 [patent_doc_number] => 20220283549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => Delay Circuit with Multiple Dependencies [patent_app_type] => utility [patent_app_number] => 17/193959 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193959
Delay circuit with multiple dependencies Mar 4, 2021 Issued
Array ( [id] => 17470655 [patent_doc_number] => 11277141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-15 [patent_title] => Dual feedback loops for integrated voltage and clock regulation [patent_app_type] => utility [patent_app_number] => 17/192403 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192403
Dual feedback loops for integrated voltage and clock regulation Mar 3, 2021 Issued
Array ( [id] => 17422831 [patent_doc_number] => 11256285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Clock generation circuit and semiconductor apparatus using the clock generation circuit [patent_app_type] => utility [patent_app_number] => 17/184282 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 23631 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184282
Clock generation circuit and semiconductor apparatus using the clock generation circuit Feb 23, 2021 Issued
Array ( [id] => 18640198 [patent_doc_number] => 11764831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Wireless bed power [patent_app_type] => utility [patent_app_number] => 17/182281 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 8261 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182281
Wireless bed power Feb 22, 2021 Issued
Array ( [id] => 17956875 [patent_doc_number] => 11482993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Mitigating the effects of kickback noise on a comparator [patent_app_type] => utility [patent_app_number] => 17/183176 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183176
Mitigating the effects of kickback noise on a comparator Feb 22, 2021 Issued
Array ( [id] => 17201429 [patent_doc_number] => 20210341524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => Timing Difference Detection Circuit Capable of Detecting a Phase Difference Between Different Channels [patent_app_type] => utility [patent_app_number] => 17/178264 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178264
Timing Difference Detection Circuit Capable of Detecting a Phase Difference Between Different Channels Feb 17, 2021 Abandoned
Array ( [id] => 17729288 [patent_doc_number] => 11385675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Multi-chip system, chip, and clock synchronization method [patent_app_type] => utility [patent_app_number] => 17/177256 [patent_app_country] => US [patent_app_date] => 2021-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/177256
Multi-chip system, chip, and clock synchronization method Feb 16, 2021 Issued
Array ( [id] => 17137454 [patent_doc_number] => 11139019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Apparatuses and methods for delay control error protection [patent_app_type] => utility [patent_app_number] => 17/177025 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 11715 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/177025
Apparatuses and methods for delay control error protection Feb 15, 2021 Issued
Array ( [id] => 17979242 [patent_doc_number] => 11496121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Combining voltage ramps to create linear voltage ramp [patent_app_type] => utility [patent_app_number] => 17/248873 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 24239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248873
Combining voltage ramps to create linear voltage ramp Feb 10, 2021 Issued
Array ( [id] => 17819107 [patent_doc_number] => 11424735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Duty correction device and method, and semiconductor apparatus using the same [patent_app_type] => utility [patent_app_number] => 17/174028 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11774 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174028 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174028
Duty correction device and method, and semiconductor apparatus using the same Feb 10, 2021 Issued
Array ( [id] => 18088372 [patent_doc_number] => 11538511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Apparatus and methods for fractional synchronization using direct digital frequency synthesis [patent_app_type] => utility [patent_app_number] => 17/173737 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 10237 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173737
Apparatus and methods for fractional synchronization using direct digital frequency synthesis Feb 10, 2021 Issued
Array ( [id] => 17194576 [patent_doc_number] => 11163328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => Clock monitoring circuit [patent_app_type] => utility [patent_app_number] => 17/151548 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10674 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151548
Clock monitoring circuit Jan 17, 2021 Issued
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