Search

Cassey D. Bauer

Examiner (ID: 11652, Phone: (571)270-7113 , Office: P/3744 )

Most Active Art Unit
3763
Art Unit(s)
3744, 3763, 3784
Total Applications
1073
Issued Applications
757
Pending Applications
106
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17869161 [patent_doc_number] => 20220291898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => ARITHMETIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/830302 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830302
ARITHMETIC DEVICE May 31, 2022 Pending
Array ( [id] => 19046462 [patent_doc_number] => 11935581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Circuit module with reliable margin configuration [patent_app_type] => utility [patent_app_number] => 17/828071 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828071 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828071
Circuit module with reliable margin configuration May 30, 2022 Issued
Array ( [id] => 19765702 [patent_doc_number] => 12224000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Fast, energy efficient 6T SRAM arrays using harvested data [patent_app_type] => utility [patent_app_number] => 17/827763 [patent_app_country] => US [patent_app_date] => 2022-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 14 [patent_no_of_words] => 5574 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827763
Fast, energy efficient 6T SRAM arrays using harvested data May 28, 2022 Issued
Array ( [id] => 19276272 [patent_doc_number] => 12026400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Memory controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/824803 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 49 [patent_no_of_words] => 46236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824803
Memory controller and operating method thereof May 24, 2022 Issued
Array ( [id] => 19370300 [patent_doc_number] => 12062390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Apparatus and method for controlling supply of power for refresh operation [patent_app_type] => utility [patent_app_number] => 17/824303 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824303
Apparatus and method for controlling supply of power for refresh operation May 24, 2022 Issued
Array ( [id] => 18562742 [patent_doc_number] => 11727992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/824758 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 22195 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824758
Semiconductor memory device May 24, 2022 Issued
Array ( [id] => 18734604 [patent_doc_number] => 11803334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Memory controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/824779 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 49 [patent_no_of_words] => 46235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824779
Memory controller and operating method thereof May 24, 2022 Issued
Array ( [id] => 18848497 [patent_doc_number] => 20230410901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => TEMPERATURE-DEPENDENT WORD LINE VOLTAGE AND DISCHARGE RATE FOR REFRESH READ OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/752524 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752524
Temperature-dependent word line voltage and discharge rate for refresh read of non-volatile memory May 23, 2022 Issued
Array ( [id] => 18935255 [patent_doc_number] => 11887693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Reconfigurable processing-in-memory logic [patent_app_type] => utility [patent_app_number] => 17/752430 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752430
Reconfigurable processing-in-memory logic May 23, 2022 Issued
Array ( [id] => 17853683 [patent_doc_number] => 20220283725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/750121 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750121
Memory controller and operating method thereof May 19, 2022 Issued
Array ( [id] => 18789052 [patent_doc_number] => 20230377664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY SUB-SYSTEM FOR MEMORY CELL TOUCH-UP [patent_app_type] => utility [patent_app_number] => 17/747761 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747761
Memory sub-system for memory cell touch-up May 17, 2022 Issued
Array ( [id] => 19093690 [patent_doc_number] => 11955154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Sense amplifier circuit with temperature compensation [patent_app_type] => utility [patent_app_number] => 17/744746 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2248 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744746
Sense amplifier circuit with temperature compensation May 15, 2022 Issued
Array ( [id] => 19237091 [patent_doc_number] => 20240194286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => Memory Structure and Memory Device [patent_app_type] => utility [patent_app_number] => 17/908477 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17908477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/908477
Memory structure and memory device May 11, 2022 Issued
Array ( [id] => 18774021 [patent_doc_number] => 20230368851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => POST-WRITE READ TECHNIQUES TO IMPROVE PROGRAMMING RELIABILITY IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/741182 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741182
Post-write read techniques to improve programming reliability in a memory device May 9, 2022 Issued
Array ( [id] => 17810590 [patent_doc_number] => 20220262425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => VERTICAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/739944 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739944 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739944
Vertical memory device May 8, 2022 Issued
Array ( [id] => 17810965 [patent_doc_number] => 20220262800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 17/737295 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737295
Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor May 4, 2022 Issued
Array ( [id] => 18950777 [patent_doc_number] => 11894080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Time-tagging read levels of multiple wordlines for open block data retention [patent_app_type] => utility [patent_app_number] => 17/733042 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 13524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733042
Time-tagging read levels of multiple wordlines for open block data retention Apr 28, 2022 Issued
Array ( [id] => 17795691 [patent_doc_number] => 20220254783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/731611 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731611
Semiconductor memory device Apr 27, 2022 Issued
Array ( [id] => 19110167 [patent_doc_number] => 11963299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Load reduced memory module [patent_app_type] => utility [patent_app_number] => 17/726354 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 14277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726354
Load reduced memory module Apr 20, 2022 Issued
Array ( [id] => 18679505 [patent_doc_number] => 20230317161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MATRIX MULTIPLICATION WITH RESISTIVE MEMORY CIRCUIT HAVING GOOD SUBSTRATE DENSITY [patent_app_type] => utility [patent_app_number] => 17/710851 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710851
MATRIX MULTIPLICATION WITH RESISTIVE MEMORY CIRCUIT HAVING GOOD SUBSTRATE DENSITY Mar 30, 2022 Abandoned
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