Search

Cassey D. Bauer

Examiner (ID: 11652, Phone: (571)270-7113 , Office: P/3744 )

Most Active Art Unit
3763
Art Unit(s)
3744, 3763, 3784
Total Applications
1073
Issued Applications
757
Pending Applications
106
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19523788 [patent_doc_number] => 12125526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Memory with bitcell power boosting [patent_app_type] => utility [patent_app_number] => 17/657231 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6155 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657231
Memory with bitcell power boosting Mar 29, 2022 Issued
Array ( [id] => 17948981 [patent_doc_number] => 20220336000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => MEMORY DEVICE GENERATING OPTIMAL WRITE VOLTAGE BASED ON SIZE OF MEMORY CELL AND INITIAL WRITE VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/707027 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707027
Memory device generating optimal write voltage based on size of memory cell and initial write voltage Mar 28, 2022 Issued
Array ( [id] => 17723594 [patent_doc_number] => 20220216316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD OF MAKING SPLIT-GATE NON-VOLATILE MEMORY CELLS WITH ERASE GATES DISPOSED OVER WORD LINE GATES [patent_app_type] => utility [patent_app_number] => 17/701840 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701840
Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates Mar 22, 2022 Issued
Array ( [id] => 17708252 [patent_doc_number] => 20220208260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MULTINARY BIT CELLS FOR MEMORY DEVICES AND NETWORK APPLICATIONS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/699253 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699253
Multinary bit cells for memory devices and network applications and method of manufacturing the same Mar 20, 2022 Issued
Array ( [id] => 18652806 [patent_doc_number] => 20230298646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DETERMINISTIC VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) MRAM WITH SPIN-TRANSFER TORQUE (STT) MRAM ASSISTANCE [patent_app_type] => utility [patent_app_number] => 17/655569 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655569
DETERMINISTIC VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) MRAM WITH SPIN-TRANSFER TORQUE (STT) MRAM ASSISTANCE Mar 20, 2022 Pending
Array ( [id] => 18528514 [patent_doc_number] => 11715512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Apparatuses and methods for dynamic targeted refresh steals [patent_app_type] => utility [patent_app_number] => 17/654035 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654035
Apparatuses and methods for dynamic targeted refresh steals Mar 7, 2022 Issued
Array ( [id] => 17763383 [patent_doc_number] => 20220236995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/680538 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680538
Apparatuses and methods for ordering bits in a memory device Feb 24, 2022 Issued
Array ( [id] => 17660481 [patent_doc_number] => 20220180946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/681401 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/681401
Memory controller and operating method thereof Feb 24, 2022 Issued
Array ( [id] => 19416547 [patent_doc_number] => 12082409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells [patent_app_type] => utility [patent_app_number] => 17/674289 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 6400 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674289
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells Feb 16, 2022 Issued
Array ( [id] => 18912880 [patent_doc_number] => 11875865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Select gate reliability [patent_app_type] => utility [patent_app_number] => 17/670111 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670111
Select gate reliability Feb 10, 2022 Issued
Array ( [id] => 17900504 [patent_doc_number] => 20220310166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/670037 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670037
In-line programming adjustment of a memory cell in a memory sub-system Feb 10, 2022 Issued
Array ( [id] => 18761545 [patent_doc_number] => 11812599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Compute near memory with backend memory [patent_app_type] => utility [patent_app_number] => 17/670248 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 14572 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670248
Compute near memory with backend memory Feb 10, 2022 Issued
Array ( [id] => 18998923 [patent_doc_number] => 11915777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Integrated assemblies and methods forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/669189 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4963 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669189
Integrated assemblies and methods forming integrated assemblies Feb 9, 2022 Issued
Array ( [id] => 18138912 [patent_doc_number] => 20230012747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => COMPILATION METHOD, COMPILATION CIRCUIT, MODE REGISTER, AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/650543 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650543
Compilation method, compilation circuit, mode register, and memory Feb 9, 2022 Issued
Array ( [id] => 18555008 [patent_doc_number] => 20230253024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => TECHNIQUES FOR MEMORY SYSTEM REFRESH [patent_app_type] => utility [patent_app_number] => 17/668197 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668197
Techniques for memory system refresh Feb 8, 2022 Issued
Array ( [id] => 19123356 [patent_doc_number] => 11967350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-23 [patent_title] => System and method for current controlled nanowire memory device [patent_app_type] => utility [patent_app_number] => 17/589739 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4220 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589739
System and method for current controlled nanowire memory device Jan 30, 2022 Issued
Array ( [id] => 17615106 [patent_doc_number] => 20220157386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SECURE ERASE FOR DATA CORRUPTION [patent_app_type] => utility [patent_app_number] => 17/589172 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589172
Secure erase for data corruption Jan 30, 2022 Issued
Array ( [id] => 18464152 [patent_doc_number] => 11688445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Valley spin hall effect based non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/588317 [patent_app_country] => US [patent_app_date] => 2022-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 33 [patent_no_of_words] => 7681 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588317
Valley spin hall effect based non-volatile memory Jan 29, 2022 Issued
Array ( [id] => 18532972 [patent_doc_number] => 20230238047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => MEMORY UNIT WITH TIME DOMAIN EDGE DELAY ACCUMULATION FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/580651 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580651
Memory unit with time domain edge delay accumulation for computing-in-memory applications and computing method thereof Jan 20, 2022 Issued
Array ( [id] => 17582616 [patent_doc_number] => 20220139471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA [patent_app_type] => utility [patent_app_number] => 17/578956 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 529 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578956
SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA Jan 18, 2022 Abandoned
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