Search

Cassey D. Bauer

Examiner (ID: 11652, Phone: (571)270-7113 , Office: P/3744 )

Most Active Art Unit
3763
Art Unit(s)
3744, 3763, 3784
Total Applications
1073
Issued Applications
757
Pending Applications
106
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20118212 [patent_doc_number] => 12367927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Pseudo-differential de-glitch sense amplifier [patent_app_type] => utility [patent_app_number] => 18/104167 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2546 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104167
Pseudo-differential de-glitch sense amplifier Jan 30, 2023 Issued
Array ( [id] => 19351297 [patent_doc_number] => 20240260261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Multi-Stack Bitcell Architecture [patent_app_type] => utility [patent_app_number] => 18/103316 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103316
Multi-Stack Bitcell Architecture Jan 29, 2023 Pending
Array ( [id] => 18424074 [patent_doc_number] => 20230178538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => TSV Coupled Integrated Circuits and Methods [patent_app_type] => utility [patent_app_number] => 18/103313 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103313
TSV Coupled Integrated Circuits and Methods Jan 29, 2023 Pending
Array ( [id] => 18424074 [patent_doc_number] => 20230178538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => TSV Coupled Integrated Circuits and Methods [patent_app_type] => utility [patent_app_number] => 18/103313 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103313
TSV Coupled Integrated Circuits and Methods Jan 29, 2023 Pending
Array ( [id] => 18424074 [patent_doc_number] => 20230178538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => TSV Coupled Integrated Circuits and Methods [patent_app_type] => utility [patent_app_number] => 18/103313 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103313
TSV Coupled Integrated Circuits and Methods Jan 29, 2023 Pending
Array ( [id] => 19351297 [patent_doc_number] => 20240260261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Multi-Stack Bitcell Architecture [patent_app_type] => utility [patent_app_number] => 18/103316 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103316
Multi-Stack Bitcell Architecture Jan 29, 2023 Pending
Array ( [id] => 18848513 [patent_doc_number] => 20230410917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => NONVOLATILE MEMORY DEVICE INCLUDING POWER GATING CIRCUIT AND INPUT/OUTPUT CIRCUIT OF A NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/100173 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100173
Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device Jan 22, 2023 Issued
Array ( [id] => 19720121 [patent_doc_number] => 12205664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory circuit and method of operating same [patent_app_type] => utility [patent_app_number] => 18/157240 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157240
Memory circuit and method of operating same Jan 19, 2023 Issued
Array ( [id] => 20161136 [patent_doc_number] => 12387769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Latency adjustment method, memory chip architecture, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/156461 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156461
Latency adjustment method, memory chip architecture, and semiconductor memory Jan 18, 2023 Issued
Array ( [id] => 20161136 [patent_doc_number] => 12387769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Latency adjustment method, memory chip architecture, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/156461 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156461
Latency adjustment method, memory chip architecture, and semiconductor memory Jan 18, 2023 Issued
Array ( [id] => 18615535 [patent_doc_number] => 20230282272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => FAST, ENERGY EFFICIENT 6T SRAM ARRAYS USING HARVESTED DATA [patent_app_type] => utility [patent_app_number] => 17/953091 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953091
FAST, ENERGY EFFICIENT 6T SRAM ARRAYS USING HARVESTED DATA Jan 9, 2023 Abandoned
Array ( [id] => 18394561 [patent_doc_number] => 20230162782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SENSE AMPLIFIER CIRCUIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/151466 [patent_app_country] => US [patent_app_date] => 2023-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151466
Sense amplifier circuit architecture Jan 7, 2023 Issued
Array ( [id] => 18361806 [patent_doc_number] => 20230143397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 18/093473 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093473
Semiconductor memory device and memory system having the same Jan 4, 2023 Issued
Array ( [id] => 19591804 [patent_doc_number] => 20240389361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME [patent_app_type] => utility [patent_app_number] => 18/572263 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18572263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/572263
NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME Jan 3, 2023 Pending
Array ( [id] => 18488149 [patent_doc_number] => 20230215497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/150164 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150164
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE Jan 3, 2023 Pending
Array ( [id] => 19734307 [patent_doc_number] => 12212315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-28 [patent_title] => Interface device [patent_app_type] => utility [patent_app_number] => 18/093281 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093281
Interface device Jan 3, 2023 Issued
Array ( [id] => 18958672 [patent_doc_number] => 20240046999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => NONVOLATILE MEMORY DEVICE PROVIDING INPUT/OUTPUT COMPATIBILITY AND METHOD FOR SETTING COMPATIBILITY THEREOF [patent_app_type] => utility [patent_app_number] => 18/148579 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148579
Nonvolatile memory device providing input/output compatibility and method for setting compatibility thereof Dec 29, 2022 Issued
Array ( [id] => 18351019 [patent_doc_number] => 20230139130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/090431 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090431
Complementary metal oxide semiconductor circuit of memory device Dec 27, 2022 Issued
Array ( [id] => 18362086 [patent_doc_number] => 20230143677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => METHODS FOR PROGRAMMING A MEMORY DEVICE, MEMORY DEVICES, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/090402 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090402
Methods for programming a memory device, memory devices, and memory systems Dec 27, 2022 Issued
Array ( [id] => 18362086 [patent_doc_number] => 20230143677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => METHODS FOR PROGRAMMING A MEMORY DEVICE, MEMORY DEVICES, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/090402 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090402
Methods for programming a memory device, memory devices, and memory systems Dec 27, 2022 Issued
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