Search

Catherine S. Branch

Examiner (ID: 14056, Phone: (571)270-3539 , Office: P/1763 )

Most Active Art Unit
1763
Art Unit(s)
1763
Total Applications
1091
Issued Applications
874
Pending Applications
86
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5481790 [patent_doc_number] => 20090204747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Non binary flash array architecture and method of operation' [patent_app_type] => utility [patent_app_number] => 12/289724 [patent_app_country] => US [patent_app_date] => 2008-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20090204747.pdf [firstpage_image] =>[orig_patent_app_number] => 12289724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289724
Non binary flash array architecture and method of operation Nov 2, 2008 Issued
Array ( [id] => 4503757 [patent_doc_number] => 07948785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Semiconductor devices having sense amplifiers and electronic systems employing the same' [patent_app_type] => utility [patent_app_number] => 12/289650 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5927 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948785.pdf [firstpage_image] =>[orig_patent_app_number] => 12289650 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289650
Semiconductor devices having sense amplifiers and electronic systems employing the same Oct 30, 2008 Issued
Array ( [id] => 4571443 [patent_doc_number] => 07839715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'SerDes double rate bitline with interlock to block precharge capture' [patent_app_type] => utility [patent_app_number] => 12/260376 [patent_app_country] => US [patent_app_date] => 2008-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1989 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/839/07839715.pdf [firstpage_image] =>[orig_patent_app_number] => 12260376 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/260376
SerDes double rate bitline with interlock to block precharge capture Oct 28, 2008 Issued
Array ( [id] => 7551945 [patent_doc_number] => 08064282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same' [patent_app_type] => utility [patent_app_number] => 12/289446 [patent_app_country] => US [patent_app_date] => 2008-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8907 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064282.pdf [firstpage_image] =>[orig_patent_app_number] => 12289446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289446
Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same Oct 27, 2008 Issued
Array ( [id] => 6433468 [patent_doc_number] => 20100103762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'Memory device and method' [patent_app_type] => utility [patent_app_number] => 12/288984 [patent_app_country] => US [patent_app_date] => 2008-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20100103762.pdf [firstpage_image] =>[orig_patent_app_number] => 12288984 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288984
Memory device and method Oct 22, 2008 Issued
Array ( [id] => 5329313 [patent_doc_number] => 20090109790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit' [patent_app_type] => utility [patent_app_number] => 12/289196 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8810 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109790.pdf [firstpage_image] =>[orig_patent_app_number] => 12289196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289196
Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit Oct 21, 2008 Issued
Array ( [id] => 4474622 [patent_doc_number] => 07944750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-17 [patent_title] => 'Multi-programmable non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 12/288762 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4952 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944750.pdf [firstpage_image] =>[orig_patent_app_number] => 12288762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288762
Multi-programmable non-volatile memory cell Oct 21, 2008 Issued
Array ( [id] => 6589215 [patent_doc_number] => 20100097853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Jeet memory cell' [patent_app_type] => utility [patent_app_number] => 12/288508 [patent_app_country] => US [patent_app_date] => 2008-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097853.pdf [firstpage_image] =>[orig_patent_app_number] => 12288508 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288508
Jeet memory cell Oct 19, 2008 Abandoned
Array ( [id] => 45016 [patent_doc_number] => 07782687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/252974 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4232 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782687.pdf [firstpage_image] =>[orig_patent_app_number] => 12252974 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/252974
Semiconductor device Oct 15, 2008 Issued
Array ( [id] => 6470186 [patent_doc_number] => 20100091559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Programmable resistance memory with feedback control' [patent_app_type] => utility [patent_app_number] => 12/287986 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12532 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091559.pdf [firstpage_image] =>[orig_patent_app_number] => 12287986 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/287986
Programmable resistance memory with feedback control Oct 14, 2008 Issued
Array ( [id] => 279056 [patent_doc_number] => 07558138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Bypass circuit for memory arrays' [patent_app_type] => utility [patent_app_number] => 12/242564 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1843 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558138.pdf [firstpage_image] =>[orig_patent_app_number] => 12242564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242564
Bypass circuit for memory arrays Sep 29, 2008 Issued
Array ( [id] => 5519981 [patent_doc_number] => 20090027962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK' [patent_app_type] => utility [patent_app_number] => 12/240280 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3436 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027962.pdf [firstpage_image] =>[orig_patent_app_number] => 12240280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240280
Multiple level cell memory device with single bit per cell, re-mappable memory block Sep 28, 2008 Issued
Array ( [id] => 5520001 [patent_doc_number] => 20090027982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'SEMICONDUCTOR MEMORY AND TEST SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/239052 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027982.pdf [firstpage_image] =>[orig_patent_app_number] => 12239052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/239052
Semiconductor memory and test system Sep 25, 2008 Issued
Array ( [id] => 6361508 [patent_doc_number] => 20100074034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'VOLTAGE REGULATOR WITH REDUCED SENSITIVITY OF OUTPUT VOLTAGE TO CHANGE IN LOAD CURRENT' [patent_app_type] => utility [patent_app_number] => 12/236382 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9226 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20100074034.pdf [firstpage_image] =>[orig_patent_app_number] => 12236382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236382
Voltage regulator with reduced sensitivity of output voltage to change in load current Sep 22, 2008 Issued
Array ( [id] => 5308840 [patent_doc_number] => 20090016121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/233278 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4638 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016121.pdf [firstpage_image] =>[orig_patent_app_number] => 12233278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233278
Semiconductor memory device and test method thereof Sep 17, 2008 Issued
Array ( [id] => 5520005 [patent_doc_number] => 20090027986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/232369 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6412 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027986.pdf [firstpage_image] =>[orig_patent_app_number] => 12232369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/232369
Semiconductor memory device Sep 15, 2008 Issued
Array ( [id] => 125580 [patent_doc_number] => 07706207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Memory with level shifting word line driver and method thereof' [patent_app_type] => utility [patent_app_number] => 12/209477 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4908 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706207.pdf [firstpage_image] =>[orig_patent_app_number] => 12209477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209477
Memory with level shifting word line driver and method thereof Sep 11, 2008 Issued
Array ( [id] => 6619707 [patent_doc_number] => 20100064114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'STACKED DEVICE IDENTIFICATION ASSIGNMENT' [patent_app_type] => utility [patent_app_number] => 12/209048 [patent_app_country] => US [patent_app_date] => 2008-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9426 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064114.pdf [firstpage_image] =>[orig_patent_app_number] => 12209048 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209048
Stacked device identification assignment Sep 10, 2008 Issued
Array ( [id] => 6587852 [patent_doc_number] => 20100321978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY CELL VOLTAGE APPLICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/747290 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321978.pdf [firstpage_image] =>[orig_patent_app_number] => 12747290 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/747290
Semiconductor memory device and memory cell voltage application method Sep 8, 2008 Issued
Array ( [id] => 7697974 [patent_doc_number] => 20110228616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency' [patent_app_type] => utility [patent_app_number] => 12/674598 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3720 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228616.pdf [firstpage_image] =>[orig_patent_app_number] => 12674598 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/674598
Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency Aug 21, 2008 Issued
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