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Catherine Witczak

Examiner (ID: 1995)

Most Active Art Unit
3767
Art Unit(s)
3767
Total Applications
400
Issued Applications
201
Pending Applications
7
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14235375 [patent_doc_number] => 20190129860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SHADOW ADDRESS SPACE FOR SHARING STORAGE [patent_app_type] => utility [patent_app_number] => 15/764855 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15764855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/764855
Shadow address space for sharing storage Oct 30, 2017 Issued
Array ( [id] => 12187651 [patent_doc_number] => 20180046587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'INFORMATION PROCESSING DEVICE AND PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/791687 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4771 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15791687 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/791687
Information processing device and processor Oct 23, 2017 Issued
Array ( [id] => 17238410 [patent_doc_number] => 11182290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Data storage device and operating method thereof for performing a garbage collection operation in consideration of a lifetime of a nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 15/785517 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4055 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785517 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785517
Data storage device and operating method thereof for performing a garbage collection operation in consideration of a lifetime of a nonvolatile memory device Oct 16, 2017 Issued
Array ( [id] => 14188793 [patent_doc_number] => 20190114102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => COMPRESSIBILITY INSTRUMENTED DYNAMIC VOLUME PROVISIONING [patent_app_type] => utility [patent_app_number] => 15/784903 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784903
Compressibility instrumented dynamic volume provisioning Oct 15, 2017 Issued
Array ( [id] => 15486031 [patent_doc_number] => 10558364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Memory allocation in a data analytics system [patent_app_type] => utility [patent_app_number] => 15/785353 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785353
Memory allocation in a data analytics system Oct 15, 2017 Issued
Array ( [id] => 17331306 [patent_doc_number] => 11221767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Cache line persistence indicator for non-volatile memory using coherence states [patent_app_type] => utility [patent_app_number] => 15/785214 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785214
Cache line persistence indicator for non-volatile memory using coherence states Oct 15, 2017 Issued
Array ( [id] => 13891645 [patent_doc_number] => 10198370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Memory distribution across multiple non-uniform memory access nodes [patent_app_type] => utility [patent_app_number] => 15/727986 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727986 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727986
Memory distribution across multiple non-uniform memory access nodes Oct 8, 2017 Issued
Array ( [id] => 12094486 [patent_doc_number] => 20170351579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'PARALLEL NODE BACKUP FOR CSV' [patent_app_type] => utility [patent_app_number] => 15/686409 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686409
Parallel node backup for CSV Aug 24, 2017 Issued
Array ( [id] => 13721741 [patent_doc_number] => 20170371825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => Method and Apparatus for Scalable Low Latency Solid State Drive Interface [patent_app_type] => utility [patent_app_number] => 15/683903 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683903
Method and Apparatus for Scalable Low Latency Solid State Drive Interface Aug 22, 2017 Abandoned
Array ( [id] => 16667235 [patent_doc_number] => 10936481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor system and method for operating the semiconductor system [patent_app_type] => utility [patent_app_number] => 15/682705 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682705 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682705
Semiconductor system and method for operating the semiconductor system Aug 21, 2017 Issued
Array ( [id] => 13992443 [patent_doc_number] => 20190065379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING EXTERNAL CACHING STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/682828 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682828
Reducing translation latency within a memory management unit using external caching structures Aug 21, 2017 Issued
Array ( [id] => 15578347 [patent_doc_number] => 10579556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Allocating address space [patent_app_type] => utility [patent_app_number] => 15/681620 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681620
Allocating address space Aug 20, 2017 Issued
Array ( [id] => 13961391 [patent_doc_number] => 20190057040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => METHODS AND SYSTEMS FOR MEMORY MANAGEMENT OF KERNEL AND USER SPACES [patent_app_type] => utility [patent_app_number] => 15/682437 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682437 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682437
Methods and systems for memory management of kernel and user spaces Aug 20, 2017 Issued
Array ( [id] => 12207561 [patent_doc_number] => 20180052787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'MEMORY SYSTEM SUPPORTING AN OFFSET COMMAND' [patent_app_type] => utility [patent_app_number] => 15/681917 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681917 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681917
MEMORY SYSTEM SUPPORTING AN OFFSET COMMAND Aug 20, 2017 Abandoned
Array ( [id] => 15789203 [patent_doc_number] => 10628326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Logical to physical mapping [patent_app_type] => utility [patent_app_number] => 15/681619 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4735 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681619
Logical to physical mapping Aug 20, 2017 Issued
Array ( [id] => 12027719 [patent_doc_number] => 20170317818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'Ensuring Information Security in Data Transfers by Dividing and Encrypting Data Blocks' [patent_app_type] => utility [patent_app_number] => 15/651085 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651085
Ensuring information security in data transfers by dividing and encrypting data blocks Jul 16, 2017 Issued
Array ( [id] => 15730697 [patent_doc_number] => 10613777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Ensuring information security in data transfers by utilizing decoy data [patent_app_type] => utility [patent_app_number] => 15/651140 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 13381 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651140
Ensuring information security in data transfers by utilizing decoy data Jul 16, 2017 Issued
Array ( [id] => 15231403 [patent_doc_number] => 10503423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => System and method for cache replacement using access-ordering lookahead approach [patent_app_type] => utility [patent_app_number] => 15/598229 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12954 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598229 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598229
System and method for cache replacement using access-ordering lookahead approach May 16, 2017 Issued
Array ( [id] => 11853673 [patent_doc_number] => 20170228165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'ESTABLISHING A LOGICAL CONFIGURATION FOR A DATA STORAGE LIBRARY' [patent_app_type] => utility [patent_app_number] => 15/494925 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4334 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494925 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/494925
Establishing a logical configuration for a data storage library Apr 23, 2017 Issued
Array ( [id] => 12393450 [patent_doc_number] => 09965399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Large-page optimization in virtual memory paging systems [patent_app_type] => utility [patent_app_number] => 15/483250 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9417 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483250
Large-page optimization in virtual memory paging systems Apr 9, 2017 Issued
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