Cathy A Maccormac
Examiner (ID: 17704)
Most Active Art Unit | 2914 |
Art Unit(s) | 2918, 2903, 2904, 2914, 2916 |
Total Applications | 5457 |
Issued Applications | 5319 |
Pending Applications | 0 |
Abandoned Applications | 138 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17295481
[patent_doc_number] => 20210391320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => Forming ESD Devices Using Multi-Gate Compatible Processes
[patent_app_type] => utility
[patent_app_number] => 17/224671
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11936
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224671
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224671 | Forming ESD devices using multi-gate compatible processes | Apr 6, 2021 | Issued |
Array
(
[id] => 17188786
[patent_doc_number] => 20210335671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/224395
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6142
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224395 | Fabrication method of semiconductor structure | Apr 6, 2021 | Issued |
Array
(
[id] => 17908759
[patent_doc_number] => 11462623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-04
[patent_title] => Semiconductor device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/222474
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 7432
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222474
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/222474 | Semiconductor device and method of forming the same | Apr 4, 2021 | Issued |
Array
(
[id] => 18520884
[patent_doc_number] => 11710779
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-25
[patent_title] => Semiconductor device including interface layer and method of fabricating thereof
[patent_app_type] => utility
[patent_app_number] => 17/301482
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7685
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301482
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/301482 | Semiconductor device including interface layer and method of fabricating thereof | Apr 4, 2021 | Issued |
Array
(
[id] => 17196131
[patent_doc_number] => 11164898
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Multilevel semiconductor device and structure
[patent_app_type] => utility
[patent_app_number] => 17/216597
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 116
[patent_no_of_words] => 18014
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216597
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/216597 | Multilevel semiconductor device and structure | Mar 28, 2021 | Issued |
Array
(
[id] => 18857301
[patent_doc_number] => 11854896
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor device with S/D bottom isolation and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/213420
[patent_app_country] => US
[patent_app_date] => 2021-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6932
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213420
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/213420 | Semiconductor device with S/D bottom isolation and methods of forming the same | Mar 25, 2021 | Issued |
Array
(
[id] => 18156250
[patent_doc_number] => 11569244
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Vertical heterostructure semiconductor memory cell and methods for making the same
[patent_app_type] => utility
[patent_app_number] => 17/199646
[patent_app_country] => US
[patent_app_date] => 2021-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 43
[patent_no_of_words] => 16220
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199646
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/199646 | Vertical heterostructure semiconductor memory cell and methods for making the same | Mar 11, 2021 | Issued |
Array
(
[id] => 18073883
[patent_doc_number] => 11532725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Method for forming sidewall spacers and semiconductor devices fabricated thereof
[patent_app_type] => utility
[patent_app_number] => 17/198777
[patent_app_country] => US
[patent_app_date] => 2021-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 61
[patent_figures_cnt] => 77
[patent_no_of_words] => 8491
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198777
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/198777 | Method for forming sidewall spacers and semiconductor devices fabricated thereof | Mar 10, 2021 | Issued |
Array
(
[id] => 17509115
[patent_doc_number] => 20220102218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => Gate Oxide Structures in Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 17/197936
[patent_app_country] => US
[patent_app_date] => 2021-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8129
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197936
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/197936 | Gate oxide structures in semiconductor devices | Mar 9, 2021 | Issued |
Array
(
[id] => 16920812
[patent_doc_number] => 20210193904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => HYBRID ULTRASONIC TRANSDUCER AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/194107
[patent_app_country] => US
[patent_app_date] => 2021-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9991
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/194107 | Hybrid ultrasonic transducer and method of forming the same | Mar 4, 2021 | Issued |
Array
(
[id] => 18549815
[patent_doc_number] => 11723186
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-08
[patent_title] => Memory cell and memory device with the same
[patent_app_type] => utility
[patent_app_number] => 17/193327
[patent_app_country] => US
[patent_app_date] => 2021-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 7773
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193327
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/193327 | Memory cell and memory device with the same | Mar 4, 2021 | Issued |
Array
(
[id] => 16951764
[patent_doc_number] => 20210210456
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH WAVEGUIDES
[patent_app_type] => utility
[patent_app_number] => 17/189201
[patent_app_country] => US
[patent_app_date] => 2021-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12502
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189201
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/189201 | Multilevel semiconductor device and structure with waveguides | Feb 28, 2021 | Issued |
Array
(
[id] => 18073894
[patent_doc_number] => 11532736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/189043
[patent_app_country] => US
[patent_app_date] => 2021-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 9286
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189043
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/189043 | Semiconductor device | Feb 28, 2021 | Issued |
Array
(
[id] => 17833625
[patent_doc_number] => 20220270929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-25
[patent_title] => METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/184835
[patent_app_country] => US
[patent_app_date] => 2021-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7109
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184835
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/184835 | Method for fabricating a semiconductor device | Feb 24, 2021 | Issued |
Array
(
[id] => 18416104
[patent_doc_number] => 11670653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Imaging device and camera system, and driving method of imaging device
[patent_app_type] => utility
[patent_app_number] => 17/173885
[patent_app_country] => US
[patent_app_date] => 2021-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 48
[patent_no_of_words] => 29331
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173885
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/173885 | Imaging device and camera system, and driving method of imaging device | Feb 10, 2021 | Issued |
Array
(
[id] => 17795838
[patent_doc_number] => 20220254930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => Transistors with Enhanced Dopant Profile and Methods for Forming the Same
[patent_app_type] => utility
[patent_app_number] => 17/173418
[patent_app_country] => US
[patent_app_date] => 2021-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10068
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173418
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/173418 | Transistors with enhanced dopant profile and methods for forming the same | Feb 10, 2021 | Issued |
Array
(
[id] => 17652898
[patent_doc_number] => 11355640
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-06-07
[patent_title] => Hybrid multi-stack semiconductor device including self-aligned channel structure and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/167640
[patent_app_country] => US
[patent_app_date] => 2021-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 28
[patent_no_of_words] => 9311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167640
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/167640 | Hybrid multi-stack semiconductor device including self-aligned channel structure and method of manufacturing the same | Feb 3, 2021 | Issued |
Array
(
[id] => 17463845
[patent_doc_number] => 20220077151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/166437
[patent_app_country] => US
[patent_app_date] => 2021-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9623
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166437
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/166437 | Memory device | Feb 2, 2021 | Issued |
Array
(
[id] => 18892763
[patent_doc_number] => 11871556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 17/158756
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 9389
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158756
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/158756 | Memory device | Jan 25, 2021 | Issued |
Array
(
[id] => 18431798
[patent_doc_number] => 11677030
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Thin-film transistor substrate and display apparatus comprising the same
[patent_app_type] => utility
[patent_app_number] => 17/158824
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 11058
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158824
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/158824 | Thin-film transistor substrate and display apparatus comprising the same | Jan 25, 2021 | Issued |