Search

Cathy Fong Fong Lam

Examiner (ID: 16371)

Most Active Art Unit
1775
Art Unit(s)
1775, 1774, 1784, 1513, CSDC, 1794, 1317, 1508
Total Applications
1786
Issued Applications
1378
Pending Applications
45
Abandoned Applications
364

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4482021 [patent_doc_number] => 07901761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Hermetic vias utilizing metal-metal oxides' [patent_app_type] => utility [patent_app_number] => 11/694774 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1762 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/901/07901761.pdf [firstpage_image] =>[orig_patent_app_number] => 11694774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694774
Hermetic vias utilizing metal-metal oxides Mar 29, 2007 Issued
Array ( [id] => 4715320 [patent_doc_number] => 20080237842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Thermally conductive molding compounds for heat dissipation in semiconductor packages' [patent_app_type] => utility [patent_app_number] => 11/729494 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2736 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237842.pdf [firstpage_image] =>[orig_patent_app_number] => 11729494 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729494
Thermally conductive molding compounds for heat dissipation in semiconductor packages Mar 28, 2007 Abandoned
Array ( [id] => 5156914 [patent_doc_number] => 20070169958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Mask for exposure' [patent_app_type] => utility [patent_app_number] => 11/728382 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1999 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20070169958.pdf [firstpage_image] =>[orig_patent_app_number] => 11728382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728382
Mask for exposure Mar 25, 2007 Abandoned
Array ( [id] => 9454832 [patent_doc_number] => 08715836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Surface-treated electro-deposited copper foil and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/282231 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 12421 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12282231 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/282231
Surface-treated electro-deposited copper foil and method for manufacturing the same Mar 8, 2007 Issued
Array ( [id] => 5004737 [patent_doc_number] => 20070202306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'CONNECTION CONFIGURATION FOR RIGID SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/679733 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5349 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20070202306.pdf [firstpage_image] =>[orig_patent_app_number] => 11679733 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679733
Connection configuration for rigid substrates Feb 26, 2007 Issued
Array ( [id] => 5253462 [patent_doc_number] => 20070134918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Bi-layer etch stop process for defect reduction and via stress migration improvement' [patent_app_type] => utility [patent_app_number] => 11/678967 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1572 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20070134918.pdf [firstpage_image] =>[orig_patent_app_number] => 11678967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678967
Bi-layer etch stop process for defect reduction and via stress migration improvement Feb 25, 2007 Issued
Array ( [id] => 5002171 [patent_doc_number] => 20070199735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Printed circuit board having inner via hole and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/709758 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3331 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20070199735.pdf [firstpage_image] =>[orig_patent_app_number] => 11709758 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709758
Printed circuit board having inner via hole and manufacturing method thereof Feb 22, 2007 Abandoned
Array ( [id] => 5005444 [patent_doc_number] => 20070203015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Ceramic dielectrics for base-metal-electrode multilayered ceramic capacitors and the preparation thereof' [patent_app_type] => utility [patent_app_number] => 11/709195 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7053 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20070203015.pdf [firstpage_image] =>[orig_patent_app_number] => 11709195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709195
Ceramic dielectrics for base-metal-electrode multilayered ceramic capacitors and the preparation thereof Feb 21, 2007 Abandoned
Array ( [id] => 4955342 [patent_doc_number] => 20080188366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Multilayer ceramic substrate and production method thereof' [patent_app_type] => utility [patent_app_number] => 11/702542 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4773 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20080188366.pdf [firstpage_image] =>[orig_patent_app_number] => 11702542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702542
Multilayer ceramic substrate Feb 5, 2007 Issued
Array ( [id] => 6536639 [patent_doc_number] => 20100044087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'PREPREG, PRINTED WIRING BOARD, MULTILAYER CIRCUIT BOARD, AND PROCESS FOR MANUFACTURING PRINTED WIRING BOARD' [patent_app_type] => utility [patent_app_number] => 12/523775 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044087.pdf [firstpage_image] =>[orig_patent_app_number] => 12523775 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/523775
Prepreg, printed wiring board, multilayer circuit board, and process for manufacturing printed wiring board Jan 24, 2007 Issued
Array ( [id] => 4764885 [patent_doc_number] => 20080176096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Solderable layer and a method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/655835 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5395 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20080176096.pdf [firstpage_image] =>[orig_patent_app_number] => 11655835 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655835
Solderable layer and a method for manufacturing the same Jan 21, 2007 Abandoned
Array ( [id] => 4805996 [patent_doc_number] => 20080169574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Direct Die Attachment' [patent_app_type] => utility [patent_app_number] => 11/622760 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3708 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20080169574.pdf [firstpage_image] =>[orig_patent_app_number] => 11622760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/622760
Direct Die Attachment Jan 11, 2007 Abandoned
Array ( [id] => 5219506 [patent_doc_number] => 20070160817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Printed circuit board and method of manufacturing semiconductor package using the same' [patent_app_type] => utility [patent_app_number] => 11/651670 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20070160817.pdf [firstpage_image] =>[orig_patent_app_number] => 11651670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651670
Printed circuit board and method of manufacturing semiconductor package using the same Jan 9, 2007 Issued
Array ( [id] => 4970988 [patent_doc_number] => 20070110990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Capacitors and methods of preparation' [patent_app_type] => utility [patent_app_number] => 11/650674 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7526 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20070110990.pdf [firstpage_image] =>[orig_patent_app_number] => 11650674 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/650674
Capacitors and methods of preparation Jan 7, 2007 Abandoned
Array ( [id] => 5079411 [patent_doc_number] => 20070122635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Bonding Structure With Buffer Layer And Method Of Forming The Same' [patent_app_type] => utility [patent_app_number] => 11/619612 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122635.pdf [firstpage_image] =>[orig_patent_app_number] => 11619612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619612
Bonding structure with buffer layer and method of forming the same Jan 3, 2007 Issued
Array ( [id] => 74949 [patent_doc_number] => 07750250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-06 [patent_title] => 'Blind via capture pad structure' [patent_app_type] => utility [patent_app_number] => 11/615467 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 6972 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/750/07750250.pdf [firstpage_image] =>[orig_patent_app_number] => 11615467 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615467
Blind via capture pad structure Dec 21, 2006 Issued
Array ( [id] => 5175244 [patent_doc_number] => 20070176302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Low temperature co-fired ceramic module and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/643693 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3504 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176302.pdf [firstpage_image] =>[orig_patent_app_number] => 11643693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643693
Low temperature co-fired ceramic module and method of manufacturing the same Dec 21, 2006 Abandoned
Array ( [id] => 4876765 [patent_doc_number] => 20080150148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHODS OF PATTERNING A DEPOSIT METAL ON A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/613368 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8968 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150148.pdf [firstpage_image] =>[orig_patent_app_number] => 11613368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613368
Methods of patterning a deposit metal on a substrate Dec 19, 2006 Issued
Array ( [id] => 4759134 [patent_doc_number] => 20080311360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Thick film circuit component and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/640498 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2112 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0311/20080311360.pdf [firstpage_image] =>[orig_patent_app_number] => 11640498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640498
Thick film circuit component and method for manufacturing the same Dec 17, 2006 Abandoned
Array ( [id] => 5264657 [patent_doc_number] => 20090117342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Method for Preparing Conductive Pattern and Conductive Pattern Prepared by the Method' [patent_app_type] => utility [patent_app_number] => 12/086613 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5533 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20090117342.pdf [firstpage_image] =>[orig_patent_app_number] => 12086613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/086613
Method for preparing conductive pattern and conductive pattern prepared by the method Dec 14, 2006 Issued
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