Search

Cathy Fong Fong Lam

Examiner (ID: 16371)

Most Active Art Unit
1775
Art Unit(s)
1775, 1774, 1784, 1513, CSDC, 1794, 1317, 1508
Total Applications
1786
Issued Applications
1378
Pending Applications
45
Abandoned Applications
364

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4242227 [patent_doc_number] => 06136419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Ceramic substrate having a sealed layer' [patent_app_type] => 1 [patent_app_number] => 9/320532 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3624 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136419.pdf [firstpage_image] =>[orig_patent_app_number] => 320532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320532
Ceramic substrate having a sealed layer May 25, 1999 Issued
Array ( [id] => 4231544 [patent_doc_number] => 06165612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Thermally conductive interface layers' [patent_app_type] => 1 [patent_app_number] => 9/312414 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3607 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165612.pdf [firstpage_image] =>[orig_patent_app_number] => 312414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312414
Thermally conductive interface layers May 13, 1999 Issued
Array ( [id] => 4290024 [patent_doc_number] => 06197407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Circuit board and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/304714 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12035 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197407.pdf [firstpage_image] =>[orig_patent_app_number] => 304714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304714
Circuit board and method of manufacturing the same May 3, 1999 Issued
Array ( [id] => 4127999 [patent_doc_number] => 06146749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Low dielectric composition, insulating material, sealing material, and circuit board' [patent_app_type] => 1 [patent_app_number] => 9/303604 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146749.pdf [firstpage_image] =>[orig_patent_app_number] => 303604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303604
Low dielectric composition, insulating material, sealing material, and circuit board May 2, 1999 Issued
Array ( [id] => 4354146 [patent_doc_number] => 06174591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Separators with direct heating medium and method for manufacturing thermally curable laminates thereof' [patent_app_type] => 1 [patent_app_number] => 9/302028 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4485 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174591.pdf [firstpage_image] =>[orig_patent_app_number] => 302028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302028
Separators with direct heating medium and method for manufacturing thermally curable laminates thereof Apr 28, 1999 Issued
Array ( [id] => 4309146 [patent_doc_number] => 06242103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method for producing laminated film/metal structures' [patent_app_type] => 1 [patent_app_number] => 9/301279 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 22 [patent_no_of_words] => 2731 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242103.pdf [firstpage_image] =>[orig_patent_app_number] => 301279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301279
Method for producing laminated film/metal structures Apr 27, 1999 Issued
Array ( [id] => 4355380 [patent_doc_number] => 06254971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Resin-having metal foil for multilayered wiring board, process for producing the same, multilayered wiring board, and electronic device' [patent_app_type] => 1 [patent_app_number] => 9/202078 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 9833 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/254/06254971.pdf [firstpage_image] =>[orig_patent_app_number] => 202078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/202078
Resin-having metal foil for multilayered wiring board, process for producing the same, multilayered wiring board, and electronic device Apr 22, 1999 Issued
Array ( [id] => 4246915 [patent_doc_number] => 06166620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Resistance wiring board and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/242425 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 40 [patent_no_of_words] => 7902 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166620.pdf [firstpage_image] =>[orig_patent_app_number] => 242425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/242425
Resistance wiring board and method for manufacturing the same Apr 7, 1999 Issued
Array ( [id] => 4279552 [patent_doc_number] => 06267797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Sintering method' [patent_app_type] => 1 [patent_app_number] => 9/214621 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2207 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/267/06267797.pdf [firstpage_image] =>[orig_patent_app_number] => 214621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/214621
Sintering method Mar 31, 1999 Issued
Array ( [id] => 4127896 [patent_doc_number] => 06146743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Barrier metallization in ceramic substrate for implantable medical devices' [patent_app_type] => 1 [patent_app_number] => 9/282131 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14648 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146743.pdf [firstpage_image] =>[orig_patent_app_number] => 282131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282131
Barrier metallization in ceramic substrate for implantable medical devices Mar 30, 1999 Issued
Array ( [id] => 4405659 [patent_doc_number] => 06228465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Process for producing multilayer wiring boards' [patent_app_type] => 1 [patent_app_number] => 9/273265 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 35 [patent_no_of_words] => 16169 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228465.pdf [firstpage_image] =>[orig_patent_app_number] => 273265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273265
Process for producing multilayer wiring boards Mar 21, 1999 Issued
Array ( [id] => 4315967 [patent_doc_number] => 06248459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon' [patent_app_type] => 1 [patent_app_number] => 9/274268 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2229 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248459.pdf [firstpage_image] =>[orig_patent_app_number] => 274268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274268
Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon Mar 21, 1999 Issued
Array ( [id] => 4422808 [patent_doc_number] => 06194788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Flip chip with integrated flux and underfill' [patent_app_type] => 1 [patent_app_number] => 9/266232 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4559 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194788.pdf [firstpage_image] =>[orig_patent_app_number] => 266232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266232
Flip chip with integrated flux and underfill Mar 9, 1999 Issued
09/257643 COMPOSITE MATERIAL USED IN MAKING PRINTED WIRING BOARDS Feb 24, 1999 Abandoned
Array ( [id] => 4265938 [patent_doc_number] => RE037085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Some uses of microencapsulation for electric paper' [patent_app_type] => 2 [patent_app_number] => 9/252852 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2152 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037085.pdf [firstpage_image] =>[orig_patent_app_number] => 252852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252852
Some uses of microencapsulation for electric paper Feb 16, 1999 Issued
Array ( [id] => 1564487 [patent_doc_number] => 06376054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Surface metallization structure for multiple chip test and burn-in' [patent_app_type] => B1 [patent_app_number] => 09/249985 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3469 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376054.pdf [firstpage_image] =>[orig_patent_app_number] => 09249985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249985
Surface metallization structure for multiple chip test and burn-in Feb 9, 1999 Issued
Array ( [id] => 4362836 [patent_doc_number] => 06274224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article' [patent_app_type] => 1 [patent_app_number] => 9/241817 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 9796 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274224.pdf [firstpage_image] =>[orig_patent_app_number] => 241817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241817
Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article Jan 31, 1999 Issued
Array ( [id] => 4282606 [patent_doc_number] => 06210805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Glass plate provided with a conductive layer, method for its production, conductive paste and window for an automobile' [patent_app_type] => 1 [patent_app_number] => 9/236573 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5547 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/210/06210805.pdf [firstpage_image] =>[orig_patent_app_number] => 236573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236573
Glass plate provided with a conductive layer, method for its production, conductive paste and window for an automobile Jan 25, 1999 Issued
Array ( [id] => 4366734 [patent_doc_number] => 06255735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers' [patent_app_type] => 1 [patent_app_number] => 9/225542 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4311 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255735.pdf [firstpage_image] =>[orig_patent_app_number] => 225542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225542
Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers Jan 4, 1999 Issued
Array ( [id] => 1544279 [patent_doc_number] => 06444295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method for improving integrated circuits bonding firmness' [patent_app_type] => B1 [patent_app_number] => 09/221569 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 3177 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444295.pdf [firstpage_image] =>[orig_patent_app_number] => 09221569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221569
Method for improving integrated circuits bonding firmness Dec 28, 1998 Issued
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