Search

Chandra P. Chaudhari

Examiner (ID: 9580, Phone: (571)272-1688 , Office: P/2898 )

Most Active Art Unit
2813
Art Unit(s)
2891, 2813, 2824, 2898, 2829, 1104, 2899
Total Applications
2684
Issued Applications
2485
Pending Applications
32
Abandoned Applications
170

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10255805 [patent_doc_number] => 20150140802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/609004 [patent_app_country] => US [patent_app_date] => 2015-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5645 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609004 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/609004
Semiconductor device and process for producing semiconductor device Jan 28, 2015 Issued
Array ( [id] => 10252212 [patent_doc_number] => 20150137208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'NAND STRING CONTAINING SELF-ALIGNED CONTROL GATE SIDEWALL CLADDING' [patent_app_type] => utility [patent_app_number] => 14/607339 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5877 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607339 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607339
NAND string containing self-aligned control gate sidewall cladding Jan 27, 2015 Issued
Array ( [id] => 10544632 [patent_doc_number] => 09269768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Insulation wall between transistors on SOI' [patent_app_type] => utility [patent_app_number] => 14/605064 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2605 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/605064
Insulation wall between transistors on SOI Jan 25, 2015 Issued
Array ( [id] => 11489539 [patent_doc_number] => 09595614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Semiconductor structures and methods with high mobility and high energy bandgap materials' [patent_app_type] => utility [patent_app_number] => 14/598378 [patent_app_country] => US [patent_app_date] => 2015-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14598378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/598378
Semiconductor structures and methods with high mobility and high energy bandgap materials Jan 15, 2015 Issued
Array ( [id] => 10268381 [patent_doc_number] => 20150153377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'SPRING-MASS SYSTEM WITH A SMALL TRANSVERSE DISPLACEMENT' [patent_app_type] => utility [patent_app_number] => 14/557614 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5293 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557614 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557614
Spring-mass system with a small transverse displacement Dec 1, 2014 Issued
Array ( [id] => 10795217 [patent_doc_number] => 20160141374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'ASPECT RATIO TRAPPING AND LATTICE ENGINEERING FOR III/V SEMICONDUCTORS' [patent_app_type] => utility [patent_app_number] => 14/541179 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541179 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541179
Aspect ratio trapping and lattice engineering for III/V semiconductors Nov 13, 2014 Issued
Array ( [id] => 10570350 [patent_doc_number] => 09293530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-22 [patent_title] => 'High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate' [patent_app_type] => utility [patent_app_number] => 14/541213 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4188 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541213 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541213
High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate Nov 13, 2014 Issued
Array ( [id] => 10795198 [patent_doc_number] => 20160141355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'ACTIVE DEVICE AND SEMICONDUCTOR DEVICE WITH THE SAME' [patent_app_type] => utility [patent_app_number] => 14/541170 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541170 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541170
Active device and semiconductor device with the same Nov 13, 2014 Issued
Array ( [id] => 10725576 [patent_doc_number] => 20160071724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'ENHANCING ELECTRICAL PROPERTY AND UV COMPATIBILITY OF ULTRATHIN BLOK BARRIER FILM' [patent_app_type] => utility [patent_app_number] => 14/535803 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14535803 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/535803
Enhancing electrical property and UV compatibility of ultrathin blok barrier film Nov 6, 2014 Issued
Array ( [id] => 10590567 [patent_doc_number] => 09312186 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-12 [patent_title] => 'Method of forming horizontal gate all around structure' [patent_app_type] => utility [patent_app_number] => 14/532074 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 7001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532074 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/532074
Method of forming horizontal gate all around structure Nov 3, 2014 Issued
Array ( [id] => 11796921 [patent_doc_number] => 09406773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/517808 [patent_app_country] => US [patent_app_date] => 2014-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 9553 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517808 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517808
Semiconductor device and method of manufacturing the same Oct 17, 2014 Issued
Array ( [id] => 9893279 [patent_doc_number] => 20150048478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 14/496430 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9283 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496430
Trench isolation for bipolar junction transistors in BiCMOS technology Sep 24, 2014 Issued
Array ( [id] => 10512824 [patent_doc_number] => 09240404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Embedded polysilicon resistor in integrated circuits formed by a replacement gate process' [patent_app_type] => utility [patent_app_number] => 14/492406 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 7202 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/492406
Embedded polysilicon resistor in integrated circuits formed by a replacement gate process Sep 21, 2014 Issued
Array ( [id] => 10132105 [patent_doc_number] => 09165946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-20 [patent_title] => 'Display panel and array substrate thereof' [patent_app_type] => utility [patent_app_number] => 14/487658 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6415 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487658 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487658
Display panel and array substrate thereof Sep 15, 2014 Issued
Array ( [id] => 11782004 [patent_doc_number] => 09391210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Top gate TFT with polymer interface control layer' [patent_app_type] => utility [patent_app_number] => 14/487184 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 52 [patent_no_of_words] => 21253 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487184 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487184
Top gate TFT with polymer interface control layer Sep 15, 2014 Issued
Array ( [id] => 10590743 [patent_doc_number] => 09312365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Manufacturing method of non-planar FET' [patent_app_type] => utility [patent_app_number] => 14/487103 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2928 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487103 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487103
Manufacturing method of non-planar FET Sep 15, 2014 Issued
Array ( [id] => 10732966 [patent_doc_number] => 20160079116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'WAFER WITH IMPROVED PLATING CURRENT DISTRIBUTION' [patent_app_type] => utility [patent_app_number] => 14/487250 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487250
Wafer with improved plating current distribution Sep 15, 2014 Issued
Array ( [id] => 10472263 [patent_doc_number] => 20150357280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'MEMORY CARD AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/482253 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2555 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482253 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/482253
MEMORY CARD AND METHOD FOR MANUFACTURING THE SAME Sep 9, 2014 Abandoned
Array ( [id] => 10974889 [patent_doc_number] => 20140377924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL' [patent_app_type] => utility [patent_app_number] => 14/481146 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8155 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481146 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481146
Strained finFET with an electrically isolated channel Sep 8, 2014 Issued
Array ( [id] => 10725623 [patent_doc_number] => 20160071771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SELF-ALIGNED QUADRUPLE PATTERNING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/477450 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477450 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477450
Self-aligned quadruple patterning process Sep 3, 2014 Issued
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