
Chandra P. Chaudhari
Examiner (ID: 9580, Phone: (571)272-1688 , Office: P/2898 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2891, 2813, 2824, 2898, 2829, 1104, 2899 |
| Total Applications | 2684 |
| Issued Applications | 2485 |
| Pending Applications | 32 |
| Abandoned Applications | 170 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13976643
[patent_doc_number] => 10217686
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => Air-cavity package with enhanced package integration level and thermal performance
[patent_app_type] => utility
[patent_app_number] => 15/935754
[patent_app_country] => US
[patent_app_date] => 2018-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8514
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935754
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/935754 | Air-cavity package with enhanced package integration level and thermal performance | Mar 25, 2018 | Issued |
Array
(
[id] => 12917872
[patent_doc_number] => 20180197800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => AIR-CAVITY PACKAGE WITH DUAL SIGNAL-TRANSITION SIDES
[patent_app_type] => utility
[patent_app_number] => 15/914448
[patent_app_country] => US
[patent_app_date] => 2018-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5814
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 432
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914448
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/914448 | Air-cavity package with dual signal-transition sides | Mar 6, 2018 | Issued |
Array
(
[id] => 13667817
[patent_doc_number] => 10164090
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Semiconductor device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/880631
[patent_app_country] => US
[patent_app_date] => 2018-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 35
[patent_no_of_words] => 12465
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880631
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/880631 | Semiconductor device and method of manufacturing the same | Jan 25, 2018 | Issued |
Array
(
[id] => 12895939
[patent_doc_number] => 20180190488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-05
[patent_title] => METHOD FOR FORMING AMORPHOUS SILICON MULTUPLE LAYER STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 15/859750
[patent_app_country] => US
[patent_app_date] => 2018-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859750
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/859750 | Method for forming amorphous silicon multuple layer structure | Jan 1, 2018 | Issued |
Array
(
[id] => 14558225
[patent_doc_number] => 10347583
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-07-09
[patent_title] => Methods of patterning dielectric layers for metallization and related structures
[patent_app_type] => utility
[patent_app_number] => 15/860193
[patent_app_country] => US
[patent_app_date] => 2018-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 3870
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860193
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/860193 | Methods of patterning dielectric layers for metallization and related structures | Jan 1, 2018 | Issued |
Array
(
[id] => 13921329
[patent_doc_number] => 10204788
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-02-12
[patent_title] => Method of forming high dielectric constant dielectric layer by atomic layer deposition
[patent_app_type] => utility
[patent_app_number] => 15/859721
[patent_app_country] => US
[patent_app_date] => 2018-01-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2809
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859721
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/859721 | Method of forming high dielectric constant dielectric layer by atomic layer deposition | Dec 31, 2017 | Issued |
Array
(
[id] => 13349521
[patent_doc_number] => 20180226300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/858403
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11823
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858403
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858403 | Semiconductor devices and methods for fabricating the same | Dec 28, 2017 | Issued |
Array
(
[id] => 12902011
[patent_doc_number] => 20180192512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-05
[patent_title] => CONDUCTIVE PATTERN AND DISPLAY DEVICE HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/858026
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16999
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -45
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858026
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858026 | Conductive pattern and display device having the same | Dec 28, 2017 | Issued |
Array
(
[id] => 14542749
[patent_doc_number] => 20190206996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => HIGH VOLTAGE DEMOS TRANSISTOR WITH IMPROVED THRESHOLD VOLTAGE MATCHING
[patent_app_type] => utility
[patent_app_number] => 15/857980
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2907
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857980
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/857980 | High voltage DEMOS transistor with improved threshold voltage matching | Dec 28, 2017 | Issued |
Array
(
[id] => 14542155
[patent_doc_number] => 20190206699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => MECHANICAL COUPLINGS DESIGNED TO RESOLVE PROCESS CONSTRAINTS
[patent_app_type] => utility
[patent_app_number] => 15/857988
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3026
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857988
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/857988 | Mechanical couplings designed to resolve process constraints | Dec 28, 2017 | Issued |
Array
(
[id] => 14430087
[patent_doc_number] => 10319859
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-11
[patent_title] => Semiconductor devices and methods of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 15/844863
[patent_app_country] => US
[patent_app_date] => 2017-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7333
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844863
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/844863 | Semiconductor devices and methods of fabricating the same | Dec 17, 2017 | Issued |
Array
(
[id] => 13222501
[patent_doc_number] => 10125014
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-13
[patent_title] => Integrated circuit package and method of forming same
[patent_app_type] => utility
[patent_app_number] => 15/843372
[patent_app_country] => US
[patent_app_date] => 2017-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 24
[patent_no_of_words] => 8079
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843372
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/843372 | Integrated circuit package and method of forming same | Dec 14, 2017 | Issued |
Array
(
[id] => 14859329
[patent_doc_number] => 10418400
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-17
[patent_title] => Imaging device
[patent_app_type] => utility
[patent_app_number] => 15/828750
[patent_app_country] => US
[patent_app_date] => 2017-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 114
[patent_no_of_words] => 30702
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828750
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/828750 | Imaging device | Nov 30, 2017 | Issued |
Array
(
[id] => 15250565
[patent_doc_number] => 10510812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-17
[patent_title] => Display-integrated infrared emitter and sensor structures
[patent_app_type] => utility
[patent_app_number] => 15/808368
[patent_app_country] => US
[patent_app_date] => 2017-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 62
[patent_no_of_words] => 12902
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808368
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/808368 | Display-integrated infrared emitter and sensor structures | Nov 8, 2017 | Issued |
Array
(
[id] => 14178105
[patent_doc_number] => 10263075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-16
[patent_title] => Nanosheet CMOS transistors
[patent_app_type] => utility
[patent_app_number] => 15/805700
[patent_app_country] => US
[patent_app_date] => 2017-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5056
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805700
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/805700 | Nanosheet CMOS transistors | Nov 6, 2017 | Issued |
Array
(
[id] => 13359889
[patent_doc_number] => 20180231484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-16
[patent_title] => CARBON NANOTUBE-BASED MULTI-SENSOR
[patent_app_type] => utility
[patent_app_number] => 15/795640
[patent_app_country] => US
[patent_app_date] => 2017-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5869
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795640
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/795640 | Carbon nanotube-based multi-sensor | Oct 26, 2017 | Issued |
Array
(
[id] => 12188788
[patent_doc_number] => 20180047723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-15
[patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/792009
[patent_app_country] => US
[patent_app_date] => 2017-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 15825
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792009
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/792009 | Method for manufacturing a semiconductor device | Oct 23, 2017 | Issued |
Array
(
[id] => 12187808
[patent_doc_number] => 20180046745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-15
[patent_title] => 'Methods for Multi-Wire Routing and Apparatus Implementing Same'
[patent_app_type] => utility
[patent_app_number] => 15/724252
[patent_app_country] => US
[patent_app_date] => 2017-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 11633
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724252
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/724252 | Methods for Multi-Wire Routing and Apparatus Implementing Same | Oct 2, 2017 | Abandoned |
Array
(
[id] => 15315803
[patent_doc_number] => 10522619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-31
[patent_title] => Three-dimensional transistor
[patent_app_type] => utility
[patent_app_number] => 15/707359
[patent_app_country] => US
[patent_app_date] => 2017-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 6489
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707359
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/707359 | Three-dimensional transistor | Sep 17, 2017 | Issued |
Array
(
[id] => 12129397
[patent_doc_number] => 20180012983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-11
[patent_title] => 'Semiconductor Device Having a Superjunction Structure'
[patent_app_type] => utility
[patent_app_number] => 15/694407
[patent_app_country] => US
[patent_app_date] => 2017-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6220
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694407
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/694407 | Semiconductor device having a superjunction structure | Aug 31, 2017 | Issued |