Search

Chandra P. Chaudhari

Examiner (ID: 9580, Phone: (571)272-1688 , Office: P/2898 )

Most Active Art Unit
2813
Art Unit(s)
2891, 2813, 2824, 2898, 2829, 1104, 2899
Total Applications
2684
Issued Applications
2485
Pending Applications
32
Abandoned Applications
170

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12162523 [patent_doc_number] => 20180033789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES' [patent_app_type] => utility [patent_app_number] => 15/224139 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224139
METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES Jul 28, 2016 Abandoned
Array ( [id] => 11932724 [patent_doc_number] => 09799728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Three-dimensional transistor and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 15/224140 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6683 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224140
Three-dimensional transistor and fabrication method thereof Jul 28, 2016 Issued
Array ( [id] => 11424819 [patent_doc_number] => 20170032964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'Method for Protecting a Surface of a Substrate and Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/215334 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5314 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215334
Method for Protecting a Surface of a Substrate and Semiconductor Device Jul 19, 2016 Abandoned
Array ( [id] => 11615591 [patent_doc_number] => 09653454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors' [patent_app_type] => utility [patent_app_number] => 15/215043 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2451 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215043
Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors Jul 19, 2016 Issued
Array ( [id] => 11932732 [patent_doc_number] => 09799736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'High acceptor level doping in silicon germanium' [patent_app_type] => utility [patent_app_number] => 15/215297 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215297 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215297
High acceptor level doping in silicon germanium Jul 19, 2016 Issued
Array ( [id] => 11904433 [patent_doc_number] => 09773875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Fabrication of silicon-germanium fin structure having silicon-rich outer surface' [patent_app_type] => utility [patent_app_number] => 15/215034 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3467 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215034 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215034
Fabrication of silicon-germanium fin structure having silicon-rich outer surface Jul 19, 2016 Issued
Array ( [id] => 11404967 [patent_doc_number] => 20170025505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'TWO-DIMENSIONAL HETEROSTRUCTURE MATERIALS' [patent_app_type] => utility [patent_app_number] => 15/215389 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13611 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215389
Two-dimensional heterostructure materials Jul 19, 2016 Issued
Array ( [id] => 13724421 [patent_doc_number] => 20170373166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH PRECISE GATE LENGTH DEFINITION [patent_app_type] => utility [patent_app_number] => 15/195332 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195332
Vertical transport field effect transistor with precise gate length definition Jun 27, 2016 Issued
Array ( [id] => 13720105 [patent_doc_number] => 20170371007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => BILAYER HARDMASK [patent_app_type] => utility [patent_app_number] => 15/195124 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195124 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195124
BILAYER HARDMASK Jun 27, 2016 Abandoned
Array ( [id] => 11637910 [patent_doc_number] => 09659895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Semi-conductor package structure' [patent_app_type] => utility [patent_app_number] => 15/195324 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2495 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195324
Semi-conductor package structure Jun 27, 2016 Issued
Array ( [id] => 11910389 [patent_doc_number] => 09779200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Methods for multi-wire routing and apparatus implementing same' [patent_app_type] => utility [patent_app_number] => 15/181157 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 11582 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/181157
Methods for multi-wire routing and apparatus implementing same Jun 12, 2016 Issued
Array ( [id] => 11132403 [patent_doc_number] => 20160329378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'ACTIVE MATRIX LIGHT EMITTING DIODES DISPLAY MODULE WITH CARBON NANOTUBES CONTROL CIRCUITS AND METHODS OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 15/169375 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169375 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169375
Active matrix light emitting diodes display module with carbon nanotubes control circuits and methods of fabrication May 30, 2016 Issued
Array ( [id] => 11315605 [patent_doc_number] => 20160351715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/135566 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135566 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135566
Semiconductor devices and methods of fabricating the same Apr 21, 2016 Issued
Array ( [id] => 11293978 [patent_doc_number] => 20160343910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/135584 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6625 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135584
Light-emitting device and method for manufacturing the same Apr 21, 2016 Issued
Array ( [id] => 12693367 [patent_doc_number] => 20180122955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 15/569283 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15569283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/569283
Semiconductor device and method for manufacturing same Apr 18, 2016 Issued
Array ( [id] => 12953437 [patent_doc_number] => 09837289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Methods for forming package-on-package structures having buffer dams [patent_app_type] => utility [patent_app_number] => 15/099236 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099236
Methods for forming package-on-package structures having buffer dams Apr 13, 2016 Issued
Array ( [id] => 11007325 [patent_doc_number] => 20160204278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'SELF-ALIGNED METAL OXIDE TFT WITH REDUCED NUMBER OF MASKS AND WITH REDUCED POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 15/080231 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7222 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15080231 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/080231
Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption Mar 23, 2016 Issued
Array ( [id] => 11725380 [patent_doc_number] => 09698247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Method of producing a semiconductor arrangement' [patent_app_type] => utility [patent_app_number] => 15/071962 [patent_app_country] => US [patent_app_date] => 2016-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 8335 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15071962 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/071962
Method of producing a semiconductor arrangement Mar 15, 2016 Issued
Array ( [id] => 13664561 [patent_doc_number] => 10162440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Array substrate, touch display apparatus and test method thereof [patent_app_type] => utility [patent_app_number] => 15/067200 [patent_app_country] => US [patent_app_date] => 2016-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067200
Array substrate, touch display apparatus and test method thereof Mar 10, 2016 Issued
Array ( [id] => 11918564 [patent_doc_number] => 09786757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Method of forming horizontal gate all around structure' [patent_app_type] => utility [patent_app_number] => 15/063601 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 7021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063601 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063601
Method of forming horizontal gate all around structure Mar 7, 2016 Issued
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