
Chandrika Prasad
Examiner (ID: 3521, Phone: (571)272-2099 , Office: P/2831 )
| Most Active Art Unit | 2839 |
| Art Unit(s) | 2833, 2831, 2839 |
| Total Applications | 2897 |
| Issued Applications | 2456 |
| Pending Applications | 55 |
| Abandoned Applications | 397 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4955033
[patent_doc_number] => 20080188057
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 12/070808
[patent_app_country] => US
[patent_app_date] => 2008-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
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[pdf_file] => publications/A1/0188/20080188057.pdf
[firstpage_image] =>[orig_patent_app_number] => 12070808
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/070808 | Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same | Feb 20, 2008 | Issued |
Array
(
[id] => 4915753
[patent_doc_number] => 20080096353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING A RECESSED GATE AND ASYMMETRIC DOPANT REGIONS AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/962099
[patent_app_country] => US
[patent_app_date] => 2007-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[firstpage_image] =>[orig_patent_app_number] => 11962099
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962099 | Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same | Dec 20, 2007 | Issued |
Array
(
[id] => 4938900
[patent_doc_number] => 20080076219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-27
[patent_title] => 'Low-K Spacer Structure for Flash Memory'
[patent_app_type] => utility
[patent_app_number] => 11/943888
[patent_app_country] => US
[patent_app_date] => 2007-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0076/20080076219.pdf
[firstpage_image] =>[orig_patent_app_number] => 11943888
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/943888 | Low-K spacer structure for flash memory | Nov 20, 2007 | Issued |
Array
(
[id] => 4938924
[patent_doc_number] => 20080076243
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-27
[patent_title] => 'Self-aligned non-volatile memory and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/984769
[patent_app_country] => US
[patent_app_date] => 2007-11-21
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11984769
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/984769 | Self-aligned non-volatile memory and method of forming the same | Nov 20, 2007 | Abandoned |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2008-03-27
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/936145
[patent_app_country] => US
[patent_app_date] => 2007-11-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/936145 | Semiconductor device and method of manufacturing same | Nov 6, 2007 | Issued |
Array
(
[id] => 4704672
[patent_doc_number] => 20080064196
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[patent_issue_date] => 2008-03-13
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/936138
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Array
(
[id] => 4704638
[patent_doc_number] => 20080064162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/931238
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 6347
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[pdf_file] => publications/A1/0064/20080064162.pdf
[firstpage_image] =>[orig_patent_app_number] => 11931238
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/931238 | Vertical SOI transistor memory cell and method of forming the same | Oct 30, 2007 | Issued |
Array
(
[id] => 151360
[patent_doc_number] => 07682914
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'Fully salicided (FUCA) MOSFET structure'
[patent_app_type] => utility
[patent_app_number] => 11/981496
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 7049
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[pdf_file] => patents/07/682/07682914.pdf
[firstpage_image] =>[orig_patent_app_number] => 11981496
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/981496 | Fully salicided (FUCA) MOSFET structure | Oct 29, 2007 | Issued |
Array
(
[id] => 7518789
[patent_doc_number] => 07972890
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-05
[patent_title] => 'Methods of manufacturing image sensors'
[patent_app_type] => utility
[patent_app_number] => 11/898578
[patent_app_country] => US
[patent_app_date] => 2007-09-13
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[pdf_file] => patents/07/972/07972890.pdf
[firstpage_image] =>[orig_patent_app_number] => 11898578
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/898578 | Methods of manufacturing image sensors | Sep 12, 2007 | Issued |
Array
(
[id] => 5195554
[patent_doc_number] => 20070294871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'Capacitor and Method of Manufacturing a Capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/851969
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[patent_app_date] => 2007-09-07
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[firstpage_image] =>[orig_patent_app_number] => 11851969
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/851969 | Capacitor and method of manufacturing a capacitor | Sep 6, 2007 | Issued |
Array
(
[id] => 121467
[patent_doc_number] => 07709331
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[patent_issue_date] => 2010-05-04
[patent_title] => 'Dual gate oxide device integration'
[patent_app_type] => utility
[patent_app_number] => 11/851719
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/851719 | Dual gate oxide device integration | Sep 6, 2007 | Issued |
Array
(
[id] => 5230917
[patent_doc_number] => 20070293025
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[patent_issue_date] => 2007-12-20
[patent_title] => 'PROTECT DIODES FOR HYBRID-ORIENTATION SUBSTRATE STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/849489
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[firstpage_image] =>[orig_patent_app_number] => 11849489
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849489 | Protect diodes for hybrid-orientation substrate structures | Sep 3, 2007 | Issued |
Array
(
[id] => 4762748
[patent_doc_number] => 20080173957
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[patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SYMMETRIC DIELECTRIC REGIONS AND STRUCTURE THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/848612 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SYMMETRIC DIELECTRIC REGIONS AND STRUCTURE THEREOF | Aug 30, 2007 | Abandoned |
Array
(
[id] => 4843220
[patent_doc_number] => 20080179628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'TRANSISTOR WITH EMBEDDED SILICON/GERMANIUM MATERIAL ON A STRAINED SEMICONDUCTOR ON INSULATOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/843358
[patent_app_country] => US
[patent_app_date] => 2007-08-22
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 43565
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[patent_title] => 'Manufacturing method of a semiconductor device'
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Array
(
[id] => 224857
[patent_doc_number] => 07605040
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[patent_issue_date] => 2009-10-20
[patent_title] => 'Method of forming high breakdown voltage low on-resistance lateral DMOS transistor'
[patent_app_type] => utility
[patent_app_number] => 11/828128
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Array
(
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[patent_issue_date] => 2010-06-10
[patent_title] => 'Brazing Method With Application of Brazing Flux On One Side Of A Section Of A Flat Tube For A Heat Exchanger'
[patent_app_type] => utility
[patent_app_number] => 12/439098
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Array
(
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[patent_title] => 'Active matrix display device and method of manufacturing the same'
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Array
(
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[patent_title] => 'SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/762944 | System and apparatus for using test structures inside of a chip during the fabrication of the chip | Jun 13, 2007 | Issued |
Array
(
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[patent_issue_date] => 2010-09-07
[patent_title] => 'Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation'
[patent_app_type] => utility
[patent_app_number] => 11/742778
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/742778 | Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation | Apr 30, 2007 | Issued |