Search

Changhyun Yi

Examiner (ID: 7260, Phone: (571)270-7799 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2812
Total Applications
1335
Issued Applications
1146
Pending Applications
153
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20299585 [patent_doc_number] => 20250324828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => DISPLAY PANEL, MANUFACTURING METHOD FOR DISPLAY PANEL, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/782412 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782412
DISPLAY PANEL, MANUFACTURING METHOD FOR DISPLAY PANEL, AND ELECTRONIC DEVICE Jul 23, 2024 Pending
Array ( [id] => 19728635 [patent_doc_number] => 20250031386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => THERMAL DISSIPATION IN STACKED MEMORY DEVICES AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/777870 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777870
THERMAL DISSIPATION IN STACKED MEMORY DEVICES AND ASSOCIATED SYSTEMS AND METHODS Jul 18, 2024 Pending
Array ( [id] => 19575458 [patent_doc_number] => 20240379750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Nanostructure Field-Effect Transistor Device and Method of Forming [patent_app_type] => utility [patent_app_number] => 18/775808 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775808
Nanostructure Field-Effect Transistor Device and Method of Forming Jul 16, 2024 Pending
Array ( [id] => 19561823 [patent_doc_number] => 20240373615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/773468 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773468
EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME Jul 14, 2024 Pending
Array ( [id] => 19546681 [patent_doc_number] => 20240363717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/771674 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771674
SEMICONDUCTOR DEVICE GATE STRUCTURES Jul 11, 2024 Pending
Array ( [id] => 19559904 [patent_doc_number] => 20240371696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Multi-Gate Field-Effect Transistors and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/771599 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771599 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771599
Multi-Gate Field-Effect Transistors and Methods of Forming the Same Jul 11, 2024 Pending
Array ( [id] => 19546715 [patent_doc_number] => 20240363751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/771551 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771551
INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES Jul 11, 2024 Pending
Array ( [id] => 20807415 [patent_doc_number] => 12672335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Backside contact structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/770393 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 5321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770393
Backside contact structures for semiconductor devices Jul 10, 2024 Issued
Array ( [id] => 19696609 [patent_doc_number] => 20250015154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => Multigate Device Having Reduced Contact Resistivity [patent_app_type] => utility [patent_app_number] => 18/769940 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769940
Multigate device having reduced contact resistivity Jul 10, 2024 Issued
Array ( [id] => 19634772 [patent_doc_number] => 20240413221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => INTEGRATED CIRCUIT DEVICE WITH IMPROVED RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/770408 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770408
INTEGRATED CIRCUIT DEVICE WITH IMPROVED RELIABILITY Jul 10, 2024 Pending
Array ( [id] => 20361748 [patent_doc_number] => 12477766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Semiconductor transistor device structure including nanostructure and gate structure with protection layer and fill layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/769168 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 50 [patent_no_of_words] => 4430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769168
Semiconductor transistor device structure including nanostructure and gate structure with protection layer and fill layer and method for forming the same Jul 9, 2024 Issued
Array ( [id] => 19546590 [patent_doc_number] => 20240363626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Self-Aligned Etch in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/766867 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766867
Semiconductor transistor devices having double-sided interconnect structures Jul 8, 2024 Issued
Array ( [id] => 20334510 [patent_doc_number] => 12464806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/766991 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766991
Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same Jul 8, 2024 Issued
Array ( [id] => 19531984 [patent_doc_number] => 20240355886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL [patent_app_type] => utility [patent_app_number] => 18/760960 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760960
Semiconductor device having a junction portion contacting a Schottky metal Jun 30, 2024 Issued
Array ( [id] => 20347615 [patent_doc_number] => 12471353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Gate-all around transistor with isolating feature under source/drain [patent_app_type] => utility [patent_app_number] => 18/759037 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 50 [patent_no_of_words] => 5853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759037 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759037
Gate-all around transistor with isolating feature under source/drain Jun 27, 2024 Issued
Array ( [id] => 20119623 [patent_doc_number] => 12369362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Forming semiconductor structures with two-dimensional materials [patent_app_type] => utility [patent_app_number] => 18/759611 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759611
Forming semiconductor structures with two-dimensional materials Jun 27, 2024 Issued
Array ( [id] => 19515938 [patent_doc_number] => 20240347624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Inner Spacer Liner [patent_app_type] => utility [patent_app_number] => 18/753469 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753469
Gate-all-around transistor having inner space lined by a semiconductor liner and method of forming the same Jun 24, 2024 Issued
Array ( [id] => 20553231 [patent_doc_number] => 12564045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor device structure with interconnect structure having air gap [patent_app_type] => utility [patent_app_number] => 18/751628 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 1202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751628
Semiconductor device structure with interconnect structure having air gap Jun 23, 2024 Issued
Array ( [id] => 19662288 [patent_doc_number] => 20240429353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SEMICONDUCTOR LIGHT-EMITTING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/748809 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748809
SEMICONDUCTOR LIGHT-EMITTING APPARATUS Jun 19, 2024 Pending
Array ( [id] => 19500432 [patent_doc_number] => 20240339450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/746928 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746928
Integrated circuit device including N-channel metal-oxide semiconductor (NMOS) transistor region and a P-channel metal-oxide semiconductor (PMOS) transistor region Jun 17, 2024 Issued
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