Search

Changhyun Yi

Examiner (ID: 7260, Phone: (571)270-7799 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2812
Total Applications
1335
Issued Applications
1146
Pending Applications
153
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19487405 [patent_doc_number] => 12107131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Gate-all-around devices having self-aligned capping between channel and backside power rail [patent_app_type] => utility [patent_app_number] => 18/328520 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 49 [patent_no_of_words] => 12623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328520
Gate-all-around devices having self-aligned capping between channel and backside power rail Jun 1, 2023 Issued
Array ( [id] => 18661531 [patent_doc_number] => 20230307545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/204469 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204469
Multi-bridge channel transistors with stacked source/drain structure and method of forming the same May 31, 2023 Issued
Array ( [id] => 19873833 [patent_doc_number] => 12266704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Semiconductor devices including horizontal gate-all-around (hGAA) nanostructure transistors and methods of forming [patent_app_type] => utility [patent_app_number] => 18/324682 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324682
Semiconductor devices including horizontal gate-all-around (hGAA) nanostructure transistors and methods of forming May 25, 2023 Issued
Array ( [id] => 19627180 [patent_doc_number] => 12166029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Integrated circuit device with power control circuit having various transistor types and method [patent_app_type] => utility [patent_app_number] => 18/323575 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 43 [patent_no_of_words] => 19596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323575
Integrated circuit device with power control circuit having various transistor types and method May 24, 2023 Issued
Array ( [id] => 19604992 [patent_doc_number] => 20240395872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR DEVICE WITH FIELD PLATE AND MULTIPLE-PART GATE STRUCTURE AND METHOD OF FABRICATION THEREFOR [patent_app_type] => utility [patent_app_number] => 18/324108 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324108
SEMICONDUCTOR DEVICE WITH FIELD PLATE AND MULTIPLE-PART GATE STRUCTURE AND METHOD OF FABRICATION THEREFOR May 24, 2023 Pending
Array ( [id] => 18653327 [patent_doc_number] => 20230299167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => BACKSIDE GATE CONTACT [patent_app_type] => utility [patent_app_number] => 18/321620 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321620 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321620
Backside gate contact May 21, 2023 Issued
Array ( [id] => 20705650 [patent_doc_number] => 12628376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Nanosheet structures with tunable channels and inner sidewall spacers [patent_app_type] => utility [patent_app_number] => 18/199054 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199054
Nanosheet structures with tunable channels and inner sidewall spacers May 17, 2023 Issued
Array ( [id] => 20637892 [patent_doc_number] => 12598788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Method to form silicon-germanium nanosheet structures [patent_app_type] => utility [patent_app_number] => 18/319857 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 86 [patent_no_of_words] => 20007 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319857
Method to form silicon-germanium nanosheet structures May 17, 2023 Issued
Array ( [id] => 20626144 [patent_doc_number] => 12593674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Semiconductor transistor device including backside contact structure vertically between backside power rail and source/drain structure and method of forming thereof [patent_app_type] => utility [patent_app_number] => 18/197381 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 58 [patent_no_of_words] => 5112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197381
Semiconductor transistor device including backside contact structure vertically between backside power rail and source/drain structure and method of forming thereof May 14, 2023 Issued
Array ( [id] => 19812461 [patent_doc_number] => 12243874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Method of forming a static random-access memory (SRAM) cell with fin field effect transistors [patent_app_type] => utility [patent_app_number] => 18/143767 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 14271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143767
Method of forming a static random-access memory (SRAM) cell with fin field effect transistors May 4, 2023 Issued
Array ( [id] => 19007739 [patent_doc_number] => 20240071810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/312811 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312811
Method of fabricating semiconductor device including organic and silicon oxide layers May 4, 2023 Issued
Array ( [id] => 20734598 [patent_doc_number] => 12641863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Semiconductor transistor structure including protection layers over isolation structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/312258 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 74 [patent_no_of_words] => 8079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312258
Semiconductor transistor structure including protection layers over isolation structure and method for forming the same May 3, 2023 Issued
Array ( [id] => 20719893 [patent_doc_number] => 12635164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Semiconductor transistor devices including nanostructures between dielectric walls and methods of manufacturing [patent_app_type] => utility [patent_app_number] => 18/311787 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 10945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311787 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311787
Semiconductor transistor devices including nanostructures between dielectric walls and methods of manufacturing May 2, 2023 Issued
Array ( [id] => 20734565 [patent_doc_number] => 12641830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Vertical self aligned gate all around transistor [patent_app_type] => utility [patent_app_number] => 18/311161 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 48 [patent_no_of_words] => 5305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311161
Vertical self aligned gate all around transistor May 1, 2023 Issued
Array ( [id] => 20649580 [patent_doc_number] => 12604543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Manufacturing method of image sensor package [patent_app_type] => utility [patent_app_number] => 18/141295 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6126 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141295
Manufacturing method of image sensor package Apr 27, 2023 Issued
Array ( [id] => 20490020 [patent_doc_number] => 20260026223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => Array Substrate, Display Panel and Display Apparatus [patent_app_type] => utility [patent_app_number] => 18/695799 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18695799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/695799
Array Substrate, Display Panel and Display Apparatus Apr 27, 2023 Pending
Array ( [id] => 19494310 [patent_doc_number] => 12113034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Vertical conductive structure surrounded by guard ring and method of making [patent_app_type] => utility [patent_app_number] => 18/138865 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138865
Vertical conductive structure surrounded by guard ring and method of making Apr 24, 2023 Issued
Array ( [id] => 19524137 [patent_doc_number] => 12125877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Nanostructure field-effect transistor device with dielectric layer for reducing substrate leakage or well isolation leakage and methods of forming [patent_app_type] => utility [patent_app_number] => 18/306629 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 54 [patent_no_of_words] => 12669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306629
Nanostructure field-effect transistor device with dielectric layer for reducing substrate leakage or well isolation leakage and methods of forming Apr 24, 2023 Issued
Array ( [id] => 19460228 [patent_doc_number] => 12100738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Semiconductor device with implant and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 18/306851 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306851
Semiconductor device with implant and method of manufacturing same Apr 24, 2023 Issued
Array ( [id] => 19531845 [patent_doc_number] => 20240355747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SUBSTRATE WITH MULTIPLE CORE LAYERS TO PROVIDE VARIED THICKNESS CAVITIES SUPPORTING VARIED THICKNESS EMBEDDED ELECTRICAL DEVICES, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 18/304195 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304195
Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods Apr 19, 2023 Issued
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