Search

Changhyun Yi

Examiner (ID: 10577, Phone: (571)270-7799 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2812
Total Applications
1322
Issued Applications
1144
Pending Applications
142
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18608109 [patent_doc_number] => 11749587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/855902 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855902
Semiconductor device Jun 30, 2022 Issued
Array ( [id] => 18857591 [patent_doc_number] => 11855188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Source/drain formation with reduced selective loss defects [patent_app_type] => utility [patent_app_number] => 17/809963 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809963
Source/drain formation with reduced selective loss defects Jun 29, 2022 Issued
Array ( [id] => 19422427 [patent_doc_number] => 20240298551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => QUANTUM DOT STRUCTURES COMPRISING AN INTEGRATED SINGLE ELECTRON TUNNELING READOUT AND SINGLE ELECTRON TUNNELING QUANTUM DOT READOUT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/574531 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18574531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/574531
QUANTUM DOT STRUCTURES COMPRISING AN INTEGRATED SINGLE ELECTRON TUNNELING READOUT AND SINGLE ELECTRON TUNNELING QUANTUM DOT READOUT STRUCTURES Jun 28, 2022 Pending
Array ( [id] => 18857403 [patent_doc_number] => 11854998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/853593 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853593
Semiconductor device and method of manufacture Jun 28, 2022 Issued
Array ( [id] => 17917889 [patent_doc_number] => 20220320285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/841217 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841217
Semiconductor device and method Jun 14, 2022 Issued
Array ( [id] => 17901190 [patent_doc_number] => 20220310852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/840737 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840737
Semiconductor devices and manufacturing methods thereof Jun 14, 2022 Issued
Array ( [id] => 19168536 [patent_doc_number] => 11984450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor device having spacer residue [patent_app_type] => utility [patent_app_number] => 17/838038 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838038
Semiconductor device having spacer residue Jun 9, 2022 Issued
Array ( [id] => 17886792 [patent_doc_number] => 20220302270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/833373 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833373
Semiconductor device structure with source/drain structure Jun 5, 2022 Issued
Array ( [id] => 18578942 [patent_doc_number] => 11735482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Semiconductor device structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/833005 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 63 [patent_no_of_words] => 10490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833005
Semiconductor device structure and methods of forming the same Jun 5, 2022 Issued
Array ( [id] => 17886820 [patent_doc_number] => 20220302298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/832930 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832930
Semiconductor device and method Jun 5, 2022 Issued
Array ( [id] => 19185254 [patent_doc_number] => 11991872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor device with gate recess and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/833396 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 8088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833396
Semiconductor device with gate recess and methods of forming the same Jun 5, 2022 Issued
Array ( [id] => 19183922 [patent_doc_number] => 11990525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/826816 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 9322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826816
Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof May 26, 2022 Issued
Array ( [id] => 19766054 [patent_doc_number] => 12224357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Semiconductor transistor device including multiple channel layers with different materials [patent_app_type] => utility [patent_app_number] => 17/804102 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804102
Semiconductor transistor device including multiple channel layers with different materials May 25, 2022 Issued
Array ( [id] => 18081301 [patent_doc_number] => 20220406913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => TRANSISTOR GATE STRUCTURE AND PROCESS [patent_app_type] => utility [patent_app_number] => 17/824491 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824491
Transistor gate structure and process May 24, 2022 Issued
Array ( [id] => 19936931 [patent_doc_number] => 12310152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Light emitting element including substrate, emission parts, insulation layer, and electrodes [patent_app_type] => utility [patent_app_number] => 17/744328 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 4550 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744328
Light emitting element including substrate, emission parts, insulation layer, and electrodes May 12, 2022 Issued
Array ( [id] => 18670089 [patent_doc_number] => 11777001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Semiconductor device including superlattice pattern [patent_app_type] => utility [patent_app_number] => 17/742985 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742985
Semiconductor device including superlattice pattern May 11, 2022 Issued
Array ( [id] => 18721680 [patent_doc_number] => 11799037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Gate-all-around integrated circuit structures having asymmetric source and drain contact structures [patent_app_type] => utility [patent_app_number] => 17/737882 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 18587 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737882
Gate-all-around integrated circuit structures having asymmetric source and drain contact structures May 4, 2022 Issued
Array ( [id] => 18548336 [patent_doc_number] => 11721697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/735114 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735114
Manufacturing method of semiconductor device May 2, 2022 Issued
Array ( [id] => 18759877 [patent_doc_number] => 11810917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Self-aligned etch in semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/733169 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 89 [patent_figures_cnt] => 124 [patent_no_of_words] => 17167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733169
Self-aligned etch in semiconductor devices Apr 28, 2022 Issued
Array ( [id] => 17780371 [patent_doc_number] => 20220246721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => CAVITY SPACER FOR NANOWIRE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/725471 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725471
Cavity spacer for nanowire transistors Apr 19, 2022 Issued
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