Search

Changhyun Yi

Examiner (ID: 7260, Phone: (571)270-7799 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2812
Total Applications
1335
Issued Applications
1146
Pending Applications
153
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20113184 [patent_doc_number] => 12363939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor device with backside power rail and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 18/610318 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 41 [patent_no_of_words] => 7842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610318
Semiconductor device with backside power rail and methods of fabrication thereof Mar 19, 2024 Issued
Array ( [id] => 19285956 [patent_doc_number] => 20240222433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/604670 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604670
Semiconductor transistor structure with nanostructures and conductive structure and method for manufacturing the same Mar 13, 2024 Issued
Array ( [id] => 19886923 [patent_doc_number] => 12272654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Method and system for fabricating fiducials using selective area growth [patent_app_type] => utility [patent_app_number] => 18/602684 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602684 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602684
Method and system for fabricating fiducials using selective area growth Mar 11, 2024 Issued
Array ( [id] => 19269636 [patent_doc_number] => 20240213340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/599779 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599779
Source/drain structure for semiconductor fin field effect transistor (finFET) device having graded germanium Mar 7, 2024 Issued
Array ( [id] => 19636510 [patent_doc_number] => 20240414959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => DISPLAY DEVICE FOR VEHICLE AND VEHICLE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/597124 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597124
DISPLAY DEVICE FOR VEHICLE AND VEHICLE INCLUDING THE SAME Mar 5, 2024 Pending
Array ( [id] => 20224742 [patent_doc_number] => 20250287673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => METHOD OF FORMING NANOSTRUCTURE DEVICE AND RELATED STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/596416 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596416
METHOD OF FORMING NANOSTRUCTURE DEVICE AND RELATED STRUCTURE Mar 4, 2024 Pending
Array ( [id] => 19470544 [patent_doc_number] => 20240324214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/595331 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595331 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595331
SEMICONDUCTOR MEMORY DEVICE Mar 3, 2024 Pending
Array ( [id] => 19255270 [patent_doc_number] => 20240206267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/591771 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591771 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591771
Display substrate having photo spacer and pixel defining layer including a plurality of openings and display device Feb 28, 2024 Issued
Array ( [id] => 19253049 [patent_doc_number] => 20240204046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Dual Side Contact Structures In Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/591290 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591290
Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming Feb 28, 2024 Issued
Array ( [id] => 19253087 [patent_doc_number] => 20240204084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/590099 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590099
Semiconductor Fin-like field-effect transistor (FinFET) device including source/drain structure with boron doped capping layer Feb 27, 2024 Issued
Array ( [id] => 19945392 [patent_doc_number] => 12317542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Semiconductor device with backside self-aligned power rail and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/588727 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 3297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588727
Semiconductor device with backside self-aligned power rail and methods of forming the same Feb 26, 2024 Issued
Array ( [id] => 19237481 [patent_doc_number] => 20240194676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => GATE ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/587622 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587622
Gate isolation structure Feb 25, 2024 Issued
Array ( [id] => 19561843 [patent_doc_number] => 20240373635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/587785 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587785
SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME Feb 25, 2024 Pending
Array ( [id] => 19887000 [patent_doc_number] => 12272733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Transistor device for source/drain backside contact and method of forming cavity [patent_app_type] => utility [patent_app_number] => 18/584028 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 11127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584028
Transistor device for source/drain backside contact and method of forming cavity Feb 21, 2024 Issued
Array ( [id] => 19733849 [patent_doc_number] => 12211851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Semiconductor device including standard cells [patent_app_type] => utility [patent_app_number] => 18/440499 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440499
Semiconductor device including standard cells Feb 12, 2024 Issued
Array ( [id] => 19221476 [patent_doc_number] => 20240186180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE DIELECTRIC LAYER HAVING AIR GAP [patent_app_type] => utility [patent_app_number] => 18/438653 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438653
Integrated circuit structure with backside dielectric layer having air gap Feb 11, 2024 Issued
Array ( [id] => 20166209 [patent_doc_number] => 20250258256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => OPTICALLY CONTROLLABLE MESOSCOPIC SPIN ORDER IN SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 18/437560 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437560
OPTICALLY CONTROLLABLE MESOSCOPIC SPIN ORDER IN SEMICONDUCTORS Feb 8, 2024 Pending
Array ( [id] => 19335695 [patent_doc_number] => 20240250125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/436052 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436052
Semiconductor device transistor having multiple channels with different widths and materials Feb 7, 2024 Issued
Array ( [id] => 19727144 [patent_doc_number] => 20250029895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SEMICONDUCTOR STACKED STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/435414 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435414
SEMICONDUCTOR STACKED STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME Feb 6, 2024 Pending
Array ( [id] => 19366060 [patent_doc_number] => 20240268094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE HAVING STACKED CAPACITOR AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/435505 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435505
SEMICONDUCTOR DEVICE HAVING STACKED CAPACITOR AND METHOD FOR FORMING THE SAME Feb 6, 2024 Pending
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