
Changhyun Yi
Examiner (ID: 7260, Phone: (571)270-7799 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826, 2812 |
| Total Applications | 1335 |
| Issued Applications | 1146 |
| Pending Applications | 153 |
| Abandoned Applications | 68 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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