
Changhyun Yi
Examiner (ID: 10577, Phone: (571)270-7799 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826, 2812 |
| Total Applications | 1322 |
| Issued Applications | 1144 |
| Pending Applications | 142 |
| Abandoned Applications | 68 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13613601
[patent_doc_number] => 20180358350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING A FLOATING ESD NODE
[patent_app_type] => utility
[patent_app_number] => 15/620207
[patent_app_country] => US
[patent_app_date] => 2017-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620207
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/620207 | Methods for an ESD protection circuit including a floating ESD node | Jun 11, 2017 | Issued |
Array
(
[id] => 12717217
[patent_doc_number] => 20180130905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/620631
[patent_app_country] => US
[patent_app_date] => 2017-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620631
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/620631 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Jun 11, 2017 | Abandoned |
Array
(
[id] => 13320907
[patent_doc_number] => 20180211991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-26
[patent_title] => LIGHT EMITTING DIODE DISPLAY AND FABRICATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/596763
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5255
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596763
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596763 | LIGHT EMITTING DIODE DISPLAY AND FABRICATING METHOD THEREOF | May 15, 2017 | Abandoned |
Array
(
[id] => 12230003
[patent_doc_number] => 09917253
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-13
[patent_title] => 'Methods of forming memory arrays'
[patent_app_type] => utility
[patent_app_number] => 15/596397
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 48
[patent_figures_cnt] => 82
[patent_no_of_words] => 7864
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596397
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596397 | Methods of forming memory arrays | May 15, 2017 | Issued |
Array
(
[id] => 14205647
[patent_doc_number] => 10269951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Semiconductor device layout and method for forming same
[patent_app_type] => utility
[patent_app_number] => 15/596977
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8720
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596977
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596977 | Semiconductor device layout and method for forming same | May 15, 2017 | Issued |
Array
(
[id] => 12062096
[patent_doc_number] => 20170338440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'FLEXIBLE DISPLAY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 15/596929
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7605
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596929
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596929 | Flexible display apparatus | May 15, 2017 | Issued |
Array
(
[id] => 13364331
[patent_doc_number] => 20180233705
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-16
[patent_title] => OLED DISPLAY DEVICE AND METHOD FOR DETECTING AND REPAIRING PACKAGING EFFECTS OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/571233
[patent_app_country] => US
[patent_app_date] => 2017-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11164
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571233
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/571233 | OLED display device and method for detecting and repairing packaging effects of the same | May 3, 2017 | Issued |
Array
(
[id] => 11869722
[patent_doc_number] => 20170237007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-17
[patent_title] => 'RF-TRANSISTORS WITH SELF-ALIGNED POINT CONTACTS'
[patent_app_type] => utility
[patent_app_number] => 15/585584
[patent_app_country] => US
[patent_app_date] => 2017-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3787
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585584
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/585584 | RF-transistors with self-aligned point contacts | May 2, 2017 | Issued |
Array
(
[id] => 11869723
[patent_doc_number] => 20170237008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-17
[patent_title] => 'RF-TRANSISTORS WITH SELF-ALIGNED POINT CONTACTS'
[patent_app_type] => utility
[patent_app_number] => 15/585616
[patent_app_country] => US
[patent_app_date] => 2017-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3786
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585616
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/585616 | RF-transistors with self-aligned point contacts | May 2, 2017 | Issued |
Array
(
[id] => 14542859
[patent_doc_number] => 20190207051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/301531
[patent_app_country] => US
[patent_app_date] => 2017-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16301531
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/301531 | Semiconductor device | May 1, 2017 | Issued |
Array
(
[id] => 13528355
[patent_doc_number] => 20180315720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/581649
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10077
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581649
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/581649 | Semiconductor structure and manufacturing method thereof | Apr 27, 2017 | Issued |
Array
(
[id] => 12174937
[patent_doc_number] => 09893085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 15/581490
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 2875
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581490
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/581490 | Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture | Apr 27, 2017 | Issued |
Array
(
[id] => 14177849
[patent_doc_number] => 10262945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-16
[patent_title] => Three-dimensional array device having a metal containing barrier and method of making thereof
[patent_app_type] => utility
[patent_app_number] => 15/581575
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 33
[patent_no_of_words] => 20540
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581575
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/581575 | Three-dimensional array device having a metal containing barrier and method of making thereof | Apr 27, 2017 | Issued |
Array
(
[id] => 12054600
[patent_doc_number] => 20170330944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-16
[patent_title] => 'NORMALLY-OFF HETROJUNCTION TRANSISTOR WITH HIGH THRESHOLD VOLTAGE'
[patent_app_type] => utility
[patent_app_number] => 15/581620
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8198
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581620
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/581620 | Normally-off hetrojunction transistor with high threshold voltage | Apr 27, 2017 | Issued |
Array
(
[id] => 14267577
[patent_doc_number] => 10283359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Systems and methods for gap filling improvement
[patent_app_type] => utility
[patent_app_number] => 15/488652
[patent_app_country] => US
[patent_app_date] => 2017-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 26
[patent_no_of_words] => 3922
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488652
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/488652 | Systems and methods for gap filling improvement | Apr 16, 2017 | Issued |
Array
(
[id] => 11839982
[patent_doc_number] => 20170221702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-03
[patent_title] => 'Method of Double Patterning Lithography Process Using Plurality of Mandrels for Integrated Circuit Applications'
[patent_app_type] => utility
[patent_app_number] => 15/489037
[patent_app_country] => US
[patent_app_date] => 2017-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4453
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489037
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/489037 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Apr 16, 2017 | Issued |
Array
(
[id] => 13293281
[patent_doc_number] => 10157841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-18
[patent_title] => Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally between a pair of structures
[patent_app_type] => utility
[patent_app_number] => 15/489311
[patent_app_country] => US
[patent_app_date] => 2017-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4581
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489311
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/489311 | Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally between a pair of structures | Apr 16, 2017 | Issued |
Array
(
[id] => 13420299
[patent_doc_number] => 20180261692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-13
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/487817
[patent_app_country] => US
[patent_app_date] => 2017-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3825
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487817
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/487817 | Semiconductor device and manufacturing method thereof | Apr 13, 2017 | Issued |
Array
(
[id] => 11997537
[patent_doc_number] => 20170301693
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-19
[patent_title] => 'RF ELECTRONIC CIRCUIT COMPRISING CAVITIES BURIED UNDER RF ELECTRONIC COMPONENTS OF THE CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/487865
[patent_app_country] => US
[patent_app_date] => 2017-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5688
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487865
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/487865 | RF electronic circuit comprising cavities buried under RF electronic components of the circuit | Apr 13, 2017 | Issued |
Array
(
[id] => 13755123
[patent_doc_number] => 10170515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Implantation process for semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/487573
[patent_app_country] => US
[patent_app_date] => 2017-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 7222
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487573
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/487573 | Implantation process for semiconductor device | Apr 13, 2017 | Issued |