Search

Changhyun Yi

Examiner (ID: 10577, Phone: (571)270-7799 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2812
Total Applications
1322
Issued Applications
1144
Pending Applications
142
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11883714 [patent_doc_number] => 09754895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-05 [patent_title] => 'Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses' [patent_app_type] => utility [patent_app_number] => 15/062452 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8412 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062452
Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses Mar 6, 2016 Issued
Array ( [id] => 11615460 [patent_doc_number] => 09653323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Manufacturing method of substrate structure having embedded interconnection layers' [patent_app_type] => utility [patent_app_number] => 15/060696 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 5588 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060696 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060696
Manufacturing method of substrate structure having embedded interconnection layers Mar 3, 2016 Issued
Array ( [id] => 14205595 [patent_doc_number] => 10269925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Manufacture method of low temperature poly-silicon TFT substrate and low temperature poly-silicon TFT substrate [patent_app_type] => utility [patent_app_number] => 15/031753 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4922 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15031753 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/031753
Manufacture method of low temperature poly-silicon TFT substrate and low temperature poly-silicon TFT substrate Feb 24, 2016 Issued
Array ( [id] => 11578724 [patent_doc_number] => 09633994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor' [patent_app_type] => utility [patent_app_number] => 15/050684 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050684 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/050684
BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor Feb 22, 2016 Issued
Array ( [id] => 10826077 [patent_doc_number] => 20160172245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'Method of forming a Gate Shield in an ED-CMOS Transistor and a base of a bipolar transistor using BICMOS Technologies' [patent_app_type] => utility [patent_app_number] => 15/050808 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/050808
Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies Feb 22, 2016 Issued
Array ( [id] => 11028670 [patent_doc_number] => 20160225626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'METHOD FOR PRODUCING A SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 15/049192 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/049192
Method for producing a semiconductor Feb 21, 2016 Issued
Array ( [id] => 11718496 [patent_doc_number] => 20170186995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DISPLAY SUBSTRATE AND FABRICATION METHOD, DISPLAY PANEL AND DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/122912 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5039 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15122912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/122912
Display substrate having driving wires and fabrication method thereof, display panel and display apparatus Feb 21, 2016 Issued
Array ( [id] => 11052214 [patent_doc_number] => 20160249174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'AUTOMATED DETECTION AND CONFIGURATION OF WEARABLE DEVICES BASED ON ON-BODY STATUS, LOCATION, AND/OR ORIENTATION' [patent_app_type] => utility [patent_app_number] => 15/048576 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 25825 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048576 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/048576
Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation Feb 18, 2016 Issued
Array ( [id] => 13225897 [patent_doc_number] => 10126721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Method and apparatus for activation and de-activation of power conditioners in distributed resource island systems using low voltage AC [patent_app_type] => utility [patent_app_number] => 15/047337 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6458 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/047337
Method and apparatus for activation and de-activation of power conditioners in distributed resource island systems using low voltage AC Feb 17, 2016 Issued
Array ( [id] => 11937627 [patent_doc_number] => 20170241777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'INERTIAL MEASUREMENT MODULE AND INERTIAL MEASUREMENT METHOD' [patent_app_type] => utility [patent_app_number] => 15/046510 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4197 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046510
INERTIAL MEASUREMENT MODULE AND INERTIAL MEASUREMENT METHOD Feb 17, 2016 Abandoned
Array ( [id] => 13212051 [patent_doc_number] => 10120394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Processing liquid supply device, processing liquid supply method, and storage medium [patent_app_type] => utility [patent_app_number] => 15/046627 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8580 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046627
Processing liquid supply device, processing liquid supply method, and storage medium Feb 17, 2016 Issued
Array ( [id] => 13264341 [patent_doc_number] => 10144243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Method for creating simulated tile wall [patent_app_type] => utility [patent_app_number] => 15/046864 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1494 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046864
Method for creating simulated tile wall Feb 17, 2016 Issued
Array ( [id] => 11831922 [patent_doc_number] => 09728672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Light emitting diode and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/045440 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2414 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045440 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045440
Light emitting diode and manufacturing method thereof Feb 16, 2016 Issued
Array ( [id] => 11883780 [patent_doc_number] => 09754961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Semiconductor memory device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 15/045526 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 8389 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045526
Semiconductor memory device and method for manufacturing same Feb 16, 2016 Issued
Array ( [id] => 13943281 [patent_doc_number] => 10207386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Determination of gain for eddy current sensor [patent_app_type] => utility [patent_app_number] => 15/046270 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046270
Determination of gain for eddy current sensor Feb 16, 2016 Issued
Array ( [id] => 11043788 [patent_doc_number] => 20160240744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'LIGHT EMITTING DIODE HAVING DISTRIBUTED BRAGG REFLECTORS (DBR) AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/045488 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3429 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045488
Light emitting diode having distributed bragg reflectors (DBR) and manufacturing method thereof Feb 16, 2016 Issued
Array ( [id] => 10814978 [patent_doc_number] => 20160161138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'HVAC CONTROL SYSTEM WITH INTERCHANGEABLE CONTROL UNITS' [patent_app_type] => utility [patent_app_number] => 15/044683 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13746 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/044683
HVAC CONTROL SYSTEM WITH INTERCHANGEABLE CONTROL UNITS Feb 15, 2016 Abandoned
Array ( [id] => 10817679 [patent_doc_number] => 20160163843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'Quantum Well Fin-Like Field Effect Transistor (QWFINFET) Having a Two-Section Combo QW Structure' [patent_app_type] => utility [patent_app_number] => 15/043962 [patent_app_country] => US [patent_app_date] => 2016-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043962 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/043962
Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure Feb 14, 2016 Issued
Array ( [id] => 10984274 [patent_doc_number] => 20160181219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'Solder Joint Structure for Ball Grid Array in Wafer Level Package' [patent_app_type] => utility [patent_app_number] => 15/044032 [patent_app_country] => US [patent_app_date] => 2016-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/044032
Solder joint structure for ball grid array in wafer level package Feb 14, 2016 Issued
Array ( [id] => 13682633 [patent_doc_number] => 20160380053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => III-V GATE-ALL-AROUND FIELD EFFECT TRANSISTOR USING ASPECT RATIO TRAPPING [patent_app_type] => utility [patent_app_number] => 15/042194 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042194
III-V gate-all-around field effect transistor using aspect ratio trapping Feb 11, 2016 Issued
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