Search

Charles Atkinson

Examiner (ID: 2446)

Most Active Art Unit
2306
Art Unit(s)
2313, 2604, 2307, 2306, 2305, 2413
Total Applications
1186
Issued Applications
1116
Pending Applications
2
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3120750 [patent_doc_number] => 05418941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Method and apparatus for a dynamic application test facility' [patent_app_type] => 1 [patent_app_number] => 8/188501 [patent_app_country] => US [patent_app_date] => 1994-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3033 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418941.pdf [firstpage_image] =>[orig_patent_app_number] => 188501 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/188501
Method and apparatus for a dynamic application test facility Jan 27, 1994 Issued
Array ( [id] => 3007553 [patent_doc_number] => 05363384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Audio signal demodulation circuit' [patent_app_type] => 1 [patent_app_number] => 8/164996 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1865 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/363/05363384.pdf [firstpage_image] =>[orig_patent_app_number] => 164996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/164996
Audio signal demodulation circuit Dec 9, 1993 Issued
Array ( [id] => 3471611 [patent_doc_number] => 05392292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Configurable spare memory chips' [patent_app_type] => 1 [patent_app_number] => 8/149967 [patent_app_country] => US [patent_app_date] => 1993-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4269 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392292.pdf [firstpage_image] =>[orig_patent_app_number] => 149967 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/149967
Configurable spare memory chips Nov 9, 1993 Issued
Array ( [id] => 3438429 [patent_doc_number] => 05416921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Apparatus and accompanying method for use in a sysplex environment for performing escalated isolation of a sysplex component in the event of a failure' [patent_app_type] => 1 [patent_app_number] => 8/147351 [patent_app_country] => US [patent_app_date] => 1993-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 26984 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416921.pdf [firstpage_image] =>[orig_patent_app_number] => 147351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/147351
Apparatus and accompanying method for use in a sysplex environment for performing escalated isolation of a sysplex component in the event of a failure Nov 2, 1993 Issued
Array ( [id] => 3126400 [patent_doc_number] => 05410546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Apparatus and method for CRC computation over fixed length blocks containing variable length packets of data received out of order' [patent_app_type] => 1 [patent_app_number] => 8/146531 [patent_app_country] => US [patent_app_date] => 1993-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 15531 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410546.pdf [firstpage_image] =>[orig_patent_app_number] => 146531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/146531
Apparatus and method for CRC computation over fixed length blocks containing variable length packets of data received out of order Oct 31, 1993 Issued
Array ( [id] => 3129159 [patent_doc_number] => 05410686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Methods for scan path debugging' [patent_app_type] => 1 [patent_app_number] => 8/143951 [patent_app_country] => US [patent_app_date] => 1993-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8563 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410686.pdf [firstpage_image] =>[orig_patent_app_number] => 143951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/143951
Methods for scan path debugging Oct 31, 1993 Issued
Array ( [id] => 3083252 [patent_doc_number] => 05337320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Semi-automatic mode of network design' [patent_app_type] => 1 [patent_app_number] => 8/141371 [patent_app_country] => US [patent_app_date] => 1993-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 29668 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/337/05337320.pdf [firstpage_image] =>[orig_patent_app_number] => 141371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141371
Semi-automatic mode of network design Oct 27, 1993 Issued
Array ( [id] => 3126092 [patent_doc_number] => 05414833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Network security system and method using a parallel finite state machine adaptive active monitor and responder' [patent_app_type] => 1 [patent_app_number] => 8/144161 [patent_app_country] => US [patent_app_date] => 1993-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 18758 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414833.pdf [firstpage_image] =>[orig_patent_app_number] => 144161 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/144161
Network security system and method using a parallel finite state machine adaptive active monitor and responder Oct 26, 1993 Issued
Array ( [id] => 3077256 [patent_doc_number] => 05353308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Event qualified test methods and circuitry' [patent_app_type] => 1 [patent_app_number] => 8/134510 [patent_app_country] => US [patent_app_date] => 1993-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 12828 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353308.pdf [firstpage_image] =>[orig_patent_app_number] => 134510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/134510
Event qualified test methods and circuitry Oct 7, 1993 Issued
Array ( [id] => 3033273 [patent_doc_number] => 05327438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Error correction system capable of correcting an error in a packet header by the use of a Reed-Solomon code' [patent_app_type] => 1 [patent_app_number] => 8/133267 [patent_app_country] => US [patent_app_date] => 1993-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7532 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327438.pdf [firstpage_image] =>[orig_patent_app_number] => 133267 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/133267
Error correction system capable of correcting an error in a packet header by the use of a Reed-Solomon code Oct 6, 1993 Issued
Array ( [id] => 3120733 [patent_doc_number] => 05418940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Method and means for detecting partial page writes and avoiding initializing new pages on DASD in a transaction management system environment' [patent_app_type] => 1 [patent_app_number] => 8/102016 [patent_app_country] => US [patent_app_date] => 1993-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5228 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418940.pdf [firstpage_image] =>[orig_patent_app_number] => 102016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/102016
Method and means for detecting partial page writes and avoiding initializing new pages on DASD in a transaction management system environment Aug 3, 1993 Issued
Array ( [id] => 3127912 [patent_doc_number] => 05396619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'System and method for testing and remapping base memory for memory diagnostics' [patent_app_type] => 1 [patent_app_number] => 8/097761 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3522 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396619.pdf [firstpage_image] =>[orig_patent_app_number] => 097761 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/097761
System and method for testing and remapping base memory for memory diagnostics Jul 25, 1993 Issued
Array ( [id] => 3060987 [patent_doc_number] => 05305324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Data scrambling interface for correcting large burst errors in high speed, high capacity tape drives' [patent_app_type] => 1 [patent_app_number] => 8/089426 [patent_app_country] => US [patent_app_date] => 1993-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3791 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305324.pdf [firstpage_image] =>[orig_patent_app_number] => 089426 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089426
Data scrambling interface for correcting large burst errors in high speed, high capacity tape drives Jul 5, 1993 Issued
Array ( [id] => 3050558 [patent_doc_number] => 05377199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Boundary test scheme for an intelligent device' [patent_app_type] => 1 [patent_app_number] => 8/085644 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3822 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377199.pdf [firstpage_image] =>[orig_patent_app_number] => 085644 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/085644
Boundary test scheme for an intelligent device Jun 29, 1993 Issued
Array ( [id] => 3433595 [patent_doc_number] => 05390327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Method for on-line reorganization of the data on a RAID-4 or RAID-5 array in the absence of one disk and the on-line restoration of a replacement disk' [patent_app_type] => 1 [patent_app_number] => 8/085021 [patent_app_country] => US [patent_app_date] => 1993-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 13406 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390327.pdf [firstpage_image] =>[orig_patent_app_number] => 085021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/085021
Method for on-line reorganization of the data on a RAID-4 or RAID-5 array in the absence of one disk and the on-line restoration of a replacement disk Jun 28, 1993 Issued
08/078491 EVENT QUALIFIED TEST METHODS AND CIRCUITRY Jun 16, 1993 Pending
08/068927 ON-LINE RESTORATION OF REDUNDANCY INFORMATION IN A REDUNDANT ARRAY SYSTEM May 27, 1993 Pending
Array ( [id] => 3435723 [patent_doc_number] => 05423029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Circuit and method for testing direct memory access circuitry' [patent_app_type] => 1 [patent_app_number] => 8/060391 [patent_app_country] => US [patent_app_date] => 1993-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3712 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/423/05423029.pdf [firstpage_image] =>[orig_patent_app_number] => 060391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/060391
Circuit and method for testing direct memory access circuitry May 10, 1993 Issued
Array ( [id] => 3433580 [patent_doc_number] => 05390326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Local area network with fault detection and recovery' [patent_app_type] => 1 [patent_app_number] => 8/056221 [patent_app_country] => US [patent_app_date] => 1993-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9689 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390326.pdf [firstpage_image] =>[orig_patent_app_number] => 056221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/056221
Local area network with fault detection and recovery Apr 29, 1993 Issued
Array ( [id] => 2949037 [patent_doc_number] => 05260948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Bidirectional boundary-scan circuit' [patent_app_type] => 1 [patent_app_number] => 8/031077 [patent_app_country] => US [patent_app_date] => 1993-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3595 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260948.pdf [firstpage_image] =>[orig_patent_app_number] => 031077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/031077
Bidirectional boundary-scan circuit Mar 10, 1993 Issued
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