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Charles Atkinson

Examiner (ID: 13902)

Most Active Art Unit
2306
Art Unit(s)
2305, 2604, 2307, 2413, 2306, 2313
Total Applications
1186
Issued Applications
1116
Pending Applications
2
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2613393 [patent_doc_number] => 04912709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-27 [patent_title] => 'Flexible VLSI on-chip maintenance and test system with unit I/O cell design' [patent_app_type] => 1 [patent_app_number] => 7/112920 [patent_app_country] => US [patent_app_date] => 1987-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6854 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/912/04912709.pdf [firstpage_image] =>[orig_patent_app_number] => 112920 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/112920
Flexible VLSI on-chip maintenance and test system with unit I/O cell design Oct 22, 1987 Issued
Array ( [id] => 2525401 [patent_doc_number] => 04852098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'Polynomial operator in galois fields and a digital signal processor comprising an operator of this type' [patent_app_type] => 1 [patent_app_number] => 7/111280 [patent_app_country] => US [patent_app_date] => 1987-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4661 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/852/04852098.pdf [firstpage_image] =>[orig_patent_app_number] => 111280 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/111280
Polynomial operator in galois fields and a digital signal processor comprising an operator of this type Oct 21, 1987 Issued
07/110140 HIGH RESOLUTION SYSTEM FOR SENSING SPATIAL COORDINATES Oct 18, 1987 Abandoned
Array ( [id] => 2495728 [patent_doc_number] => 04866714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-12 [patent_title] => 'Personal computer-based dynamic burn-in system' [patent_app_type] => 1 [patent_app_number] => 7/108672 [patent_app_country] => US [patent_app_date] => 1987-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 23789 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/866/04866714.pdf [firstpage_image] =>[orig_patent_app_number] => 108672 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/108672
Personal computer-based dynamic burn-in system Oct 14, 1987 Issued
Array ( [id] => 2528278 [patent_doc_number] => 04870646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-26 [patent_title] => 'Word synchronizer' [patent_app_type] => 1 [patent_app_number] => 7/106292 [patent_app_country] => US [patent_app_date] => 1987-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2476 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/870/04870646.pdf [firstpage_image] =>[orig_patent_app_number] => 106292 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/106292
Word synchronizer Oct 8, 1987 Issued
Array ( [id] => 2522007 [patent_doc_number] => 04841525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-20 [patent_title] => 'Method and arrangement for testing mega-bit memory modules with arbitrary test patterns in a multi-bit test mode' [patent_app_type] => 1 [patent_app_number] => 7/104155 [patent_app_country] => US [patent_app_date] => 1987-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1927 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/841/04841525.pdf [firstpage_image] =>[orig_patent_app_number] => 104155 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/104155
Method and arrangement for testing mega-bit memory modules with arbitrary test patterns in a multi-bit test mode Oct 4, 1987 Issued
Array ( [id] => 2533375 [patent_doc_number] => 04873688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'High-speed real-time Reed-Solomon decoder' [patent_app_type] => 1 [patent_app_number] => 7/105401 [patent_app_country] => US [patent_app_date] => 1987-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9435 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873688.pdf [firstpage_image] =>[orig_patent_app_number] => 105401 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/105401
High-speed real-time Reed-Solomon decoder Oct 4, 1987 Issued
Array ( [id] => 2499664 [patent_doc_number] => 04868828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Architecture for time or transform domain decoding of reed-solomon codes' [patent_app_type] => 1 [patent_app_number] => 7/105101 [patent_app_country] => US [patent_app_date] => 1987-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9069 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868828.pdf [firstpage_image] =>[orig_patent_app_number] => 105101 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/105101
Architecture for time or transform domain decoding of reed-solomon codes Oct 4, 1987 Issued
Array ( [id] => 2531582 [patent_doc_number] => 04881230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-14 [patent_title] => 'Expert system for processing errors in a multiplex communications system' [patent_app_type] => 1 [patent_app_number] => 7/105772 [patent_app_country] => US [patent_app_date] => 1987-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 84 [patent_no_of_words] => 43394 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/881/04881230.pdf [firstpage_image] =>[orig_patent_app_number] => 105772 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/105772
Expert system for processing errors in a multiplex communications system Oct 4, 1987 Issued
Array ( [id] => 2533357 [patent_doc_number] => 04873687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Failing resource manager in a multiplex communication system' [patent_app_type] => 1 [patent_app_number] => 7/105771 [patent_app_country] => US [patent_app_date] => 1987-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 84 [patent_no_of_words] => 43193 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873687.pdf [firstpage_image] =>[orig_patent_app_number] => 105771 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/105771
Failing resource manager in a multiplex communication system Oct 4, 1987 Issued
90/001340 AUTOMATIC SHUNT DEVICE Sep 27, 1987 Issued
Array ( [id] => 2478430 [patent_doc_number] => 04845717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-04 [patent_title] => 'IC card having two output buffers' [patent_app_type] => 1 [patent_app_number] => 7/100762 [patent_app_country] => US [patent_app_date] => 1987-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 4271 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/845/04845717.pdf [firstpage_image] =>[orig_patent_app_number] => 100762 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/100762
IC card having two output buffers Sep 23, 1987 Issued
Array ( [id] => 2568770 [patent_doc_number] => 04853930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-01 [patent_title] => 'Error-correcting bit-serial decoder' [patent_app_type] => 1 [patent_app_number] => 7/099801 [patent_app_country] => US [patent_app_date] => 1987-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 11864 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/853/04853930.pdf [firstpage_image] =>[orig_patent_app_number] => 099801 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/099801
Error-correcting bit-serial decoder Sep 21, 1987 Issued
Array ( [id] => 2504683 [patent_doc_number] => 04847840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-11 [patent_title] => 'Digital data error block detection and display device' [patent_app_type] => 1 [patent_app_number] => 7/096760 [patent_app_country] => US [patent_app_date] => 1987-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 11980 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/847/04847840.pdf [firstpage_image] =>[orig_patent_app_number] => 096760 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/096760
Digital data error block detection and display device Sep 8, 1987 Issued
Array ( [id] => 2422868 [patent_doc_number] => 04742521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-03 [patent_title] => 'Bar cord information input confirming method' [patent_app_type] => 1 [patent_app_number] => 7/094094 [patent_app_country] => US [patent_app_date] => 1987-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2217 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/742/04742521.pdf [firstpage_image] =>[orig_patent_app_number] => 094094 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/094094
Bar cord information input confirming method Sep 3, 1987 Issued
Array ( [id] => 2699249 [patent_doc_number] => 05050170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Apparatus for combining signals from first and second information processing elements' [patent_app_type] => 1 [patent_app_number] => 7/093840 [patent_app_country] => US [patent_app_date] => 1987-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4705 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/050/05050170.pdf [firstpage_image] =>[orig_patent_app_number] => 093840 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/093840
Apparatus for combining signals from first and second information processing elements Sep 3, 1987 Issued
Array ( [id] => 2504664 [patent_doc_number] => 04847839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-11 [patent_title] => 'Digital registers with serial accessed mode control bit' [patent_app_type] => 1 [patent_app_number] => 7/089381 [patent_app_country] => US [patent_app_date] => 1987-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2762 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/847/04847839.pdf [firstpage_image] =>[orig_patent_app_number] => 089381 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/089381
Digital registers with serial accessed mode control bit Aug 25, 1987 Issued
Array ( [id] => 2573402 [patent_doc_number] => 04849977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'D-5 Channel bank control structure and controller' [patent_app_type] => 1 [patent_app_number] => 7/086013 [patent_app_country] => US [patent_app_date] => 1987-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4774 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849977.pdf [firstpage_image] =>[orig_patent_app_number] => 086013 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/086013
D-5 Channel bank control structure and controller Aug 16, 1987 Issued
Array ( [id] => 2742780 [patent_doc_number] => 04998252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'Method and apparatus for transmitting digital data' [patent_app_type] => 1 [patent_app_number] => 7/082331 [patent_app_country] => US [patent_app_date] => 1987-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/998/04998252.pdf [firstpage_image] =>[orig_patent_app_number] => 082331 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/082331
Method and apparatus for transmitting digital data Aug 5, 1987 Issued
Array ( [id] => 2562283 [patent_doc_number] => 04833676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-23 [patent_title] => 'Interleaved method and circuitry for testing for stuck open faults' [patent_app_type] => 1 [patent_app_number] => 7/079372 [patent_app_country] => US [patent_app_date] => 1987-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 0 [patent_no_of_words] => 2180 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/833/04833676.pdf [firstpage_image] =>[orig_patent_app_number] => 079372 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079372
Interleaved method and circuitry for testing for stuck open faults Jul 29, 1987 Issued
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