Search

Charles C. Jiang

Supervisory Patent Examiner (ID: 15054, Phone: (571)270-7191 , Office: P/2412 )

Most Active Art Unit
2472
Art Unit(s)
2472, 2412, 2416
Total Applications
301
Issued Applications
212
Pending Applications
23
Abandoned Applications
71

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19075572 [patent_doc_number] => 11944917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Media synchronized control of peripherals [patent_app_type] => utility [patent_app_number] => 17/528393 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528393
Media synchronized control of peripherals Nov 16, 2021 Issued
Array ( [id] => 18802940 [patent_doc_number] => 11836097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Memory device for adjusting memory capacity per channel and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/229198 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229198
Memory device for adjusting memory capacity per channel and memory system including the same Apr 12, 2021 Issued
Array ( [id] => 17892293 [patent_doc_number] => 11455264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Minimizing delay while migrating direct memory access (DMA) mapped pages [patent_app_type] => utility [patent_app_number] => 16/989248 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7969 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989248
Minimizing delay while migrating direct memory access (DMA) mapped pages Aug 9, 2020 Issued
Array ( [id] => 17091773 [patent_doc_number] => 11119963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Modular system architecture for supporting multiple solid-state drives [patent_app_type] => utility [patent_app_number] => 16/844689 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844689
Modular system architecture for supporting multiple solid-state drives Apr 8, 2020 Issued
Array ( [id] => 16193904 [patent_doc_number] => 20200234753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MEMORY DEVICES CONFIGURED TO PROVIDE EXTERNAL REGULATED VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/838473 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838473
Memory devices configured to provide external regulated voltages Apr 1, 2020 Issued
Array ( [id] => 17729540 [patent_doc_number] => 11385927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Interrupt servicing in userspace [patent_app_type] => utility [patent_app_number] => 16/737786 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737786
Interrupt servicing in userspace Jan 7, 2020 Issued
Array ( [id] => 15837255 [patent_doc_number] => 20200133910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => PROGRAMMED DELAY FOR RFFE BUS TRIGGERS [patent_app_type] => utility [patent_app_number] => 16/590879 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590879 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590879
PROGRAMMED DELAY FOR RFFE BUS TRIGGERS Oct 1, 2019 Abandoned
Array ( [id] => 17715409 [patent_doc_number] => 11379400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Extension apparatus for universal serial bus interface [patent_app_type] => utility [patent_app_number] => 16/521669 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4340 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521669
Extension apparatus for universal serial bus interface Jul 24, 2019 Issued
Array ( [id] => 17622017 [patent_doc_number] => 11341073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Redundant paths to single port storage devices [patent_app_type] => utility [patent_app_number] => 16/451584 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6687 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451584
Redundant paths to single port storage devices Jun 24, 2019 Issued
Array ( [id] => 16788121 [patent_doc_number] => 10990554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Mechanism to identify FPGA and SSD pairing in a multi-device environment [patent_app_type] => utility [patent_app_number] => 16/435442 [patent_app_country] => US [patent_app_date] => 2019-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 16658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435442
Mechanism to identify FPGA and SSD pairing in a multi-device environment Jun 6, 2019 Issued
Array ( [id] => 18087198 [patent_doc_number] => 11537330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Selectively improving raid operations latency [patent_app_type] => utility [patent_app_number] => 16/428378 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428378
Selectively improving raid operations latency May 30, 2019 Issued
Array ( [id] => 14842609 [patent_doc_number] => 20190279705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => MEMORY DEVICES CONFIGURED TO PROVIDE EXTERNAL REGULATED VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/423427 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423427 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423427
Memory devices configured to provide external regulated voltages May 27, 2019 Issued
Array ( [id] => 16666791 [patent_doc_number] => 10936034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Information handling system multiple port power source management [patent_app_type] => utility [patent_app_number] => 16/398805 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6904 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398805
Information handling system multiple port power source management Apr 29, 2019 Issued
Array ( [id] => 15122753 [patent_doc_number] => 20190348010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => ELECTRONIC DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/370033 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370033
Electronic device and control method thereof Mar 28, 2019 Issued
Array ( [id] => 18872866 [patent_doc_number] => 11860672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/260087 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 28101 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/260087
Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD Jan 27, 2019 Issued
Array ( [id] => 14188979 [patent_doc_number] => 20190114195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => VIRTUAL DEVICE COMPOSITION IN A SCALABLE INPUT/OUTPUT (I/O) VIRTUALIZATION (S-IOV) ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/211941 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211941
VIRTUAL DEVICE COMPOSITION IN A SCALABLE INPUT/OUTPUT (I/O) VIRTUALIZATION (S-IOV) ARCHITECTURE Dec 5, 2018 Abandoned
Array ( [id] => 14076951 [patent_doc_number] => 20190087363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MULTILEVEL MEMORY BUS SYSTEM [patent_app_type] => utility [patent_app_number] => 16/197001 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197001 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197001
Multilevel memory bus system Nov 19, 2018 Issued
Array ( [id] => 15120371 [patent_doc_number] => 20190346818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHOD FOR CONFIGURING INPUT AND OUTPUT INTERFACES, I/O INTERFACE CONFIGURATION DEVICE AND CONTROL SYSTEM [patent_app_type] => utility [patent_app_number] => 16/131085 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16131085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/131085
Method for configuring input and output interfaces, I/O interface configuration device and control system Sep 13, 2018 Issued
Array ( [id] => 14719959 [patent_doc_number] => 20190251043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => MEMORY DEVICE FOR ADJUSTING MEMORY CAPACITY PER CHANNEL AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/115089 [patent_app_country] => US [patent_app_date] => 2018-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16115089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/115089
Memory device for adjusting memory capacity per channel and memory system including the same Aug 27, 2018 Issued
Array ( [id] => 14840651 [patent_doc_number] => 20190278726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR APPARATUS, COMMAND TRAINING SYSTEM, AND COMMAND TRAINING METHOD [patent_app_type] => utility [patent_app_number] => 16/113846 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113846
Semiconductor apparatus, command training system, and command training method Aug 26, 2018 Issued
Menu