Search

Charles Chiang Chow

Examiner (ID: 5644)

Most Active Art Unit
2618
Art Unit(s)
2685, 2649, 2741, 2618, 2749, 2684
Total Applications
615
Issued Applications
432
Pending Applications
47
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 707587 [patent_doc_number] => 07060547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Method for forming a junction region of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/764437 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1812 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/060/07060547.pdf [firstpage_image] =>[orig_patent_app_number] => 10764437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764437
Method for forming a junction region of a semiconductor device Jan 26, 2004 Issued
Array ( [id] => 7127493 [patent_doc_number] => 20050059237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/761187 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4221 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20050059237.pdf [firstpage_image] =>[orig_patent_app_number] => 10761187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761187
Method for manufacturing semiconductor device Jan 21, 2004 Issued
Array ( [id] => 7677545 [patent_doc_number] => 20040152281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Semiconductor device having element isolation structure' [patent_app_type] => new [patent_app_number] => 10/760357 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3976 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152281.pdf [firstpage_image] =>[orig_patent_app_number] => 10760357 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760357
Semiconductor device having element isolation structure Jan 20, 2004 Abandoned
Array ( [id] => 7677588 [patent_doc_number] => 20040152238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Flip chip interconnection using no-clean flux' [patent_app_type] => new [patent_app_number] => 10/762013 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4041 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152238.pdf [firstpage_image] =>[orig_patent_app_number] => 10762013 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762013
Flip chip interconnection using no-clean flux Jan 20, 2004 Abandoned
Array ( [id] => 534312 [patent_doc_number] => 07172948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Method to avoid a laser marked area step height' [patent_app_type] => utility [patent_app_number] => 10/761657 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2716 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/172/07172948.pdf [firstpage_image] =>[orig_patent_app_number] => 10761657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761657
Method to avoid a laser marked area step height Jan 19, 2004 Issued
Array ( [id] => 7039564 [patent_doc_number] => 20050158963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Method of forming planarized shallow trench isolation' [patent_app_type] => utility [patent_app_number] => 10/759207 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2202 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158963.pdf [firstpage_image] =>[orig_patent_app_number] => 10759207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759207
Method of forming planarized shallow trench isolation Jan 19, 2004 Abandoned
Array ( [id] => 7287313 [patent_doc_number] => 20040147108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Fill material for dual damascene processes' [patent_app_type] => new [patent_app_number] => 10/759447 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10872 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147108.pdf [firstpage_image] =>[orig_patent_app_number] => 10759447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759447
Fill material for dual damascene processes Jan 15, 2004 Issued
Array ( [id] => 7287318 [patent_doc_number] => 20040147113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Method for manufacturing conductive layer and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/757167 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14126 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147113.pdf [firstpage_image] =>[orig_patent_app_number] => 10757167 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757167
Method of manufacturing semiconductor device Jan 12, 2004 Issued
Array ( [id] => 7429958 [patent_doc_number] => 20040266163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Bumping process' [patent_app_type] => new [patent_app_number] => 10/753317 [patent_app_country] => US [patent_app_date] => 2004-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2327 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266163.pdf [firstpage_image] =>[orig_patent_app_number] => 10753317 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753317
Bumping process Jan 8, 2004 Issued
Array ( [id] => 6983473 [patent_doc_number] => 20050153543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method of forming self aligned contact' [patent_app_type] => utility [patent_app_number] => 10/753657 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153543.pdf [firstpage_image] =>[orig_patent_app_number] => 10753657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753657
Method of forming self aligned contact Jan 7, 2004 Abandoned
Array ( [id] => 7074894 [patent_doc_number] => 20050148162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases' [patent_app_type] => utility [patent_app_number] => 10/751207 [patent_app_country] => US [patent_app_date] => 2004-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3807 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148162.pdf [firstpage_image] =>[orig_patent_app_number] => 10751207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/751207
Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases Jan 1, 2004 Abandoned
Array ( [id] => 7174370 [patent_doc_number] => 20040201097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/747317 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8036 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20040201097.pdf [firstpage_image] =>[orig_patent_app_number] => 10747317 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747317
Semiconductor device and method for manufacturing the same Dec 29, 2003 Issued
Array ( [id] => 740965 [patent_doc_number] => 07029979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Methods for manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/749647 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1239 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/029/07029979.pdf [firstpage_image] =>[orig_patent_app_number] => 10749647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749647
Methods for manufacturing semiconductor devices Dec 29, 2003 Issued
Array ( [id] => 7309310 [patent_doc_number] => 20040142553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Methods of manufacturing semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/746837 [patent_app_country] => US [patent_app_date] => 2003-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1996 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142553.pdf [firstpage_image] =>[orig_patent_app_number] => 10746837 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746837
Methods of manufacturing semiconductor devices Dec 25, 2003 Issued
Array ( [id] => 5616185 [patent_doc_number] => 20060185717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Photoelectric conversion element and process for fabricating the same, electronic apparatus and process for fabricating the same, and semiconductor layer and process for forming the same' [patent_app_type] => utility [patent_app_number] => 10/543050 [patent_app_country] => US [patent_app_date] => 2003-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7850 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20060185717.pdf [firstpage_image] =>[orig_patent_app_number] => 10543050 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/543050
Photoelectric conversion element and process for fabricating the same, electronic apparatus and process for fabricating the same, and semiconductor layer and process for forming the same Dec 25, 2003 Issued
Array ( [id] => 5745070 [patent_doc_number] => 20060107994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Photoelectric conversion element and process for fabricating the same, electronic device and process for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/541877 [patent_app_country] => US [patent_app_date] => 2003-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8629 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107994.pdf [firstpage_image] =>[orig_patent_app_number] => 10541877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/541877
Photoelectric conversion element and process for fabricating the same, electronic device and process for fabricating the same Dec 24, 2003 Issued
Array ( [id] => 7324238 [patent_doc_number] => 20040137715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Methods of manufacturing semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/744717 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 572 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137715.pdf [firstpage_image] =>[orig_patent_app_number] => 10744717 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744717
Methods of manufacturing semiconductor devices Dec 22, 2003 Abandoned
Array ( [id] => 701477 [patent_doc_number] => 07064027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance' [patent_app_type] => utility [patent_app_number] => 10/713227 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 31 [patent_no_of_words] => 4186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064027.pdf [firstpage_image] =>[orig_patent_app_number] => 10713227 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713227
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance Nov 12, 2003 Issued
Array ( [id] => 7192937 [patent_doc_number] => 20050040847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Process for producing a nanoelement arrangement, and nanoelement arrangement' [patent_app_type] => utility [patent_app_number] => 10/712767 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4268 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040847.pdf [firstpage_image] =>[orig_patent_app_number] => 10712767 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712767
Process for producing a nanoelement arrangement, and nanoelement arrangement Nov 11, 2003 Issued
Array ( [id] => 999534 [patent_doc_number] => 06911384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Gate structure with independently tailored vertical doping profile' [patent_app_type] => utility [patent_app_number] => 10/605697 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2627 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911384.pdf [firstpage_image] =>[orig_patent_app_number] => 10605697 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605697
Gate structure with independently tailored vertical doping profile Oct 20, 2003 Issued
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