Charles Chiang Chow

Array ( [id] => 7620073 [patent_doc_number] => 06943110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Wafer processing apparatus and methods for depositing cobalt silicide' [patent_app_type] => utility [patent_app_number] => 10/640779 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 6248 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943110.pdf [firstpage_image] =>[orig_patent_app_number] => 10640779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7269964 [patent_doc_number] => 20040058482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Method for improving a semiconductor substrate having SiGe film and semiconductor device manufactured by using this method' [patent_app_type] => new [patent_app_number] => 10/639647 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058482.pdf [firstpage_image] =>[orig_patent_app_number] => 10639647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 701411 [patent_doc_number] => 07063992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Semiconductor substrate surface preparation using high temperature convection heating' [patent_app_type] => utility [patent_app_number] => 10/637447 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3082 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/063/07063992.pdf [firstpage_image] =>[orig_patent_app_number] => 10637447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7154788 [patent_doc_number] => 20050026409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Method for forming DRAM cell bit line and bit line contact structure' [patent_app_type] => utility [patent_app_number] => 10/628507 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1247 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026409.pdf [firstpage_image] =>[orig_patent_app_number] => 10628507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7287305 [patent_doc_number] => 20040147101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Surface preparation prior to deposition' [patent_app_type] => new [patent_app_number] => 10/626217 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9578 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147101.pdf [firstpage_image] =>[orig_patent_app_number] => 10626217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7324158 [patent_doc_number] => 20040137663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Method of reducing internal stress in materials' [patent_app_type] => new [patent_app_number] => 10/624427 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3847 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137663.pdf [firstpage_image] =>[orig_patent_app_number] => 10624427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 715360 [patent_doc_number] => 07052922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Stable electroless fine pitch interconnect plating' [patent_app_type] => utility [patent_app_number] => 10/622497 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3310 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052922.pdf [firstpage_image] =>[orig_patent_app_number] => 10622497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7675159 [patent_doc_number] => 20040126959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Method of manufacturing ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/620927 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2118 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20040126959.pdf [firstpage_image] =>[orig_patent_app_number] => 10620927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1005329 [patent_doc_number] => 06905923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Offset spacer process for forming N-type transistors' [patent_app_type] => utility [patent_app_number] => 10/619877 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4871 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905923.pdf [firstpage_image] =>[orig_patent_app_number] => 10619877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7399159 [patent_doc_number] => 20040018747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Deposition method of a dielectric layer' [patent_app_type] => new [patent_app_number] => 10/617767 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3833 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018747.pdf [firstpage_image] =>[orig_patent_app_number] => 10617767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7089122 [patent_doc_number] => 20050009235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method of forming a scribe line on a ceramic substrate' [patent_app_type] => utility [patent_app_number] => 10/618377 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009235.pdf [firstpage_image] =>[orig_patent_app_number] => 10618377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7203705 [patent_doc_number] => 20040087081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Capacitor fabrication methods and capacitor structures including niobium oxide' [patent_app_type] => new [patent_app_number] => 10/611797 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7076 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087081.pdf [firstpage_image] =>[orig_patent_app_number] => 10611797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1050036 [patent_doc_number] => 06861313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Semiconductor memory device and fabrication method thereof using damascene bitline process' [patent_app_type] => utility [patent_app_number] => 10/607597 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 4212 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861313.pdf [firstpage_image] =>[orig_patent_app_number] => 10607597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7312648 [patent_doc_number] => 20040033444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Method of manufacturing semiconductor device and method of forming pattern' [patent_app_type] => new [patent_app_number] => 10/603077 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10664 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033444.pdf [firstpage_image] =>[orig_patent_app_number] => 10603077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7408753 [patent_doc_number] => 20040106249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Method to fabricate dual metal CMOS devices' [patent_app_type] => new [patent_app_number] => 10/601037 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6222 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106249.pdf [firstpage_image] =>[orig_patent_app_number] => 10601037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1085653 [patent_doc_number] => 06830998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Gate dielectric quality for replacement metal gate transistors' [patent_app_type] => B1 [patent_app_number] => 10/462667 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2480 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/830/06830998.pdf [firstpage_image] =>[orig_patent_app_number] => 10462667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1113695 [patent_doc_number] => 06803608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Light emitting diode used as an illuminant of an image sensor' [patent_app_type] => B1 [patent_app_number] => 10/457317 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2132 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803608.pdf [firstpage_image] =>[orig_patent_app_number] => 10457317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 985510 [patent_doc_number] => 06924238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Edge peeling improvement of low-k dielectric materials stack by adjusting EBR resistance' [patent_app_type] => utility [patent_app_number] => 10/455037 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924238.pdf [firstpage_image] =>[orig_patent_app_number] => 10455037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 972110 [patent_doc_number] => 06936495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Method of making an optoelectronic semiconductor package device' [patent_app_type] => utility [patent_app_number] => 10/447517 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 53 [patent_no_of_words] => 11034 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936495.pdf [firstpage_image] =>[orig_patent_app_number] => 10447517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 931122 [patent_doc_number] => 06979626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method for fabricating a self-aligned bipolar transistor having increased manufacturability and related structure' [patent_app_type] => utility [patent_app_number] => 10/442449 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5804 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979626.pdf [firstpage_image] =>[orig_patent_app_number] => 10442449 [rel_patent_id] =>[rel_patent_doc_number] =>)