Search

Charles Chiang Chow

Examiner (ID: 5644)

Most Active Art Unit
2618
Art Unit(s)
2685, 2649, 2741, 2618, 2749, 2684
Total Applications
615
Issued Applications
432
Pending Applications
47
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1167762 [patent_doc_number] => 06759710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques' [patent_app_type] => B2 [patent_app_number] => 10/051562 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 51 [patent_no_of_words] => 5475 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759710.pdf [firstpage_image] =>[orig_patent_app_number] => 10051562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051562
Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques Jan 17, 2002 Issued
Array ( [id] => 1288495 [patent_doc_number] => 06632688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method for evaluating impurity concentrations in epitaxial reagent gases' [patent_app_type] => B2 [patent_app_number] => 10/003961 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2793 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632688.pdf [firstpage_image] =>[orig_patent_app_number] => 10003961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003961
Method for evaluating impurity concentrations in epitaxial reagent gases Nov 13, 2001 Issued
Array ( [id] => 1580912 [patent_doc_number] => 06423556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method for evaluating impurity concentrations in heat treatment furnaces' [patent_app_type] => B1 [patent_app_number] => 10/003994 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2924 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423556.pdf [firstpage_image] =>[orig_patent_app_number] => 10003994 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003994
Method for evaluating impurity concentrations in heat treatment furnaces Nov 13, 2001 Issued
Array ( [id] => 5986181 [patent_doc_number] => 20020098601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Method for evaluating impurity concentrations in unpolished wafers grown by the Czochralski method' [patent_app_type] => new [patent_app_number] => 10/004065 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1791 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098601.pdf [firstpage_image] =>[orig_patent_app_number] => 10004065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004065
Method for evaluating impurity concentrations in unpolished wafers grown by the Czochralski method Nov 13, 2001 Issued
Array ( [id] => 1273599 [patent_doc_number] => 06649427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method for evaluating impurity concentrations in epitaxial susceptors' [patent_app_type] => B2 [patent_app_number] => 10/003960 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2871 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649427.pdf [firstpage_image] =>[orig_patent_app_number] => 10003960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003960
Method for evaluating impurity concentrations in epitaxial susceptors Nov 13, 2001 Issued
10/009386 REFLECTIVE LAYER BURIED IN SILICON AND METHOD OF FABRICATION Nov 4, 2001 Abandoned
Array ( [id] => 1278004 [patent_doc_number] => 06645860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Adhesion promotion method for CVD copper metallization in IC applications' [patent_app_type] => B2 [patent_app_number] => 10/002886 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6438 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645860.pdf [firstpage_image] =>[orig_patent_app_number] => 10002886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002886
Adhesion promotion method for CVD copper metallization in IC applications Oct 31, 2001 Issued
Array ( [id] => 5986524 [patent_doc_number] => 20020098712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Multi-thickness oxide growth with in-situ scanned laser heating' [patent_app_type] => new [patent_app_number] => 09/982657 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2194 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098712.pdf [firstpage_image] =>[orig_patent_app_number] => 09982657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/982657
Multi-thickness oxide growth with in-situ scanned laser heating Oct 17, 2001 Abandoned
Array ( [id] => 5870549 [patent_doc_number] => 20020047131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Selective placement of quantum wells in flipchip light emitting diodes for improved light extraction' [patent_app_type] => new [patent_app_number] => 09/977144 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4232 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047131.pdf [firstpage_image] =>[orig_patent_app_number] => 09977144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977144
Selective placement of quantum wells in flipchip light emitting diodes for improved light extraction Oct 10, 2001 Abandoned
Array ( [id] => 1395971 [patent_doc_number] => 06531328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Packaging of light-emitting diode' [patent_app_type] => B1 [patent_app_number] => 09/973777 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 2846 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531328.pdf [firstpage_image] =>[orig_patent_app_number] => 09973777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973777
Packaging of light-emitting diode Oct 10, 2001 Issued
Array ( [id] => 6783093 [patent_doc_number] => 20030064540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Procedure for encapsulation of electronic devices' [patent_app_type] => new [patent_app_number] => 09/968567 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2198 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20030064540.pdf [firstpage_image] =>[orig_patent_app_number] => 09968567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968567
Procedure for encapsulation of electronic devices Sep 27, 2001 Issued
Array ( [id] => 1273703 [patent_doc_number] => 06649447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Methods for plastic injection molding, with particular applicability in facilitating use of high density lead frames' [patent_app_type] => B1 [patent_app_number] => 09/965214 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3657 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649447.pdf [firstpage_image] =>[orig_patent_app_number] => 09965214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965214
Methods for plastic injection molding, with particular applicability in facilitating use of high density lead frames Sep 25, 2001 Issued
Array ( [id] => 6674362 [patent_doc_number] => 20030059965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method for screening semiconductor devices for contact coplanarity' [patent_app_type] => new [patent_app_number] => 09/962407 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3932 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20030059965.pdf [firstpage_image] =>[orig_patent_app_number] => 09962407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962407
Method for screening semiconductor devices for contact coplanarity Sep 24, 2001 Issued
Array ( [id] => 968473 [patent_doc_number] => 06939747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-06 [patent_title] => 'Multiple selectable function integrated circuit module' [patent_app_type] => utility [patent_app_number] => 09/961767 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939747.pdf [firstpage_image] =>[orig_patent_app_number] => 09961767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961767
Multiple selectable function integrated circuit module Sep 20, 2001 Issued
Array ( [id] => 6290288 [patent_doc_number] => 20020055191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Dielectric element including oxide-based dielectric film and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 09/956817 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7531 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055191.pdf [firstpage_image] =>[orig_patent_app_number] => 09956817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956817
Dielectric element including oxide-based dielectric film and method of fabricating the same Sep 20, 2001 Issued
Array ( [id] => 7465112 [patent_doc_number] => 20040053434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Microelectronic mechanical system and methods' [patent_app_type] => new [patent_app_number] => 09/952626 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7453 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053434.pdf [firstpage_image] =>[orig_patent_app_number] => 09952626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952626
Microelectronic mechanical system and methods Sep 12, 2001 Issued
Array ( [id] => 1216519 [patent_doc_number] => 06706622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Bonding pad interface' [patent_app_type] => B1 [patent_app_number] => 09/949207 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1835 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/706/06706622.pdf [firstpage_image] =>[orig_patent_app_number] => 09949207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949207
Bonding pad interface Sep 6, 2001 Issued
Array ( [id] => 1371370 [patent_doc_number] => 06562670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Poly-silicon thin film transistor and method for fabricating thereof' [patent_app_type] => B2 [patent_app_number] => 09/927797 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1885 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562670.pdf [firstpage_image] =>[orig_patent_app_number] => 09927797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927797
Poly-silicon thin film transistor and method for fabricating thereof Aug 9, 2001 Issued
Array ( [id] => 6723501 [patent_doc_number] => 20030205813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'METHOD OF FORMING A MULTI-LAYERED WIRING STRUCTURE INCORPORATION IN SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE AND HAVING LARGE ELECTROMIGRATION RESISTANCE.' [patent_app_type] => new [patent_app_number] => 09/922737 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4459 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205813.pdf [firstpage_image] =>[orig_patent_app_number] => 09922737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922737
METHOD OF FORMING A MULTI-LAYERED WIRING STRUCTURE INCORPORATION IN SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE AND HAVING LARGE ELECTROMIGRATION RESISTANCE. Aug 6, 2001 Abandoned
Array ( [id] => 1253314 [patent_doc_number] => 06670236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Semiconductor device having capacitance element and method of producing the same' [patent_app_type] => B2 [patent_app_number] => 09/924047 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4762 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670236.pdf [firstpage_image] =>[orig_patent_app_number] => 09924047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924047
Semiconductor device having capacitance element and method of producing the same Aug 6, 2001 Issued
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