Search

Charles Chiang Chow

Examiner (ID: 5644)

Most Active Art Unit
2618
Art Unit(s)
2685, 2649, 2741, 2618, 2749, 2684
Total Applications
615
Issued Applications
432
Pending Applications
47
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6415080 [patent_doc_number] => 20020125515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Field effect transistor using zirconiumtitanate thin film' [patent_app_type] => new [patent_app_number] => 09/920637 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3081 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125515.pdf [firstpage_image] =>[orig_patent_app_number] => 09920637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920637
Field effect transistor using zirconiumtitanate thin film Aug 2, 2001 Abandoned
Array ( [id] => 6571903 [patent_doc_number] => 20020014634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/911397 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10556 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014634.pdf [firstpage_image] =>[orig_patent_app_number] => 09911397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911397
Semiconductor device having a gate insulating film comprising a metal oxide and method of manufacturing the same Jul 24, 2001 Issued
Array ( [id] => 1040601 [patent_doc_number] => 06869899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Lateral-only photoresist trimming for sub-80 nm gate stack' [patent_app_type] => utility [patent_app_number] => 09/902727 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3351 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869899.pdf [firstpage_image] =>[orig_patent_app_number] => 09902727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902727
Lateral-only photoresist trimming for sub-80 nm gate stack Jul 11, 2001 Issued
Array ( [id] => 5874136 [patent_doc_number] => 20020048951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method for manufacturing a chip scale package' [patent_app_type] => new [patent_app_number] => 09/891116 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3490 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048951.pdf [firstpage_image] =>[orig_patent_app_number] => 09891116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891116
Method for manufacturing a chip scale package Jun 24, 2001 Abandoned
Array ( [id] => 6921574 [patent_doc_number] => 20010029059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Chip photoelectric sensor assembly and method for making same' [patent_app_type] => new [patent_app_number] => 09/881757 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1273 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029059.pdf [firstpage_image] =>[orig_patent_app_number] => 09881757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881757
Chip photoelectric sensor assembly and method for making same Jun 17, 2001 Issued
Array ( [id] => 6921589 [patent_doc_number] => 20010029074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Semiconductor device and process of producing the same' [patent_app_type] => new [patent_app_number] => 09/876457 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4957 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029074.pdf [firstpage_image] =>[orig_patent_app_number] => 09876457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/876457
Semiconductor device and process of producing the same Jun 5, 2001 Abandoned
Array ( [id] => 1248125 [patent_doc_number] => 06673633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method of forming patterned thin film and method of manufacturing thin-film magnetic head' [patent_app_type] => B2 [patent_app_number] => 09/870737 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 28 [patent_no_of_words] => 9174 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673633.pdf [firstpage_image] =>[orig_patent_app_number] => 09870737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870737
Method of forming patterned thin film and method of manufacturing thin-film magnetic head May 31, 2001 Issued
Array ( [id] => 1270157 [patent_doc_number] => 06653197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method for fabricating capacitor of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/867657 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1719 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653197.pdf [firstpage_image] =>[orig_patent_app_number] => 09867657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867657
Method for fabricating capacitor of semiconductor device May 30, 2001 Issued
Array ( [id] => 1205579 [patent_doc_number] => 06716717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method for fabricating capacitor of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/867527 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1801 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716717.pdf [firstpage_image] =>[orig_patent_app_number] => 09867527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867527
Method for fabricating capacitor of semiconductor device May 30, 2001 Issued
Array ( [id] => 6447079 [patent_doc_number] => 20020177264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Reducing threshold voltage roll-up/roll-off effect for MOSFETS' [patent_app_type] => new [patent_app_number] => 09/866397 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1882 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177264.pdf [firstpage_image] =>[orig_patent_app_number] => 09866397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866397
Reducing threshold voltage roll-up/roll-off effect for MOSFETS May 24, 2001 Abandoned
Array ( [id] => 5874074 [patent_doc_number] => 20020048897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method of forming a self-aligned shallow trench isolation' [patent_app_type] => new [patent_app_number] => 09/864627 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2831 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048897.pdf [firstpage_image] =>[orig_patent_app_number] => 09864627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864627
Method of forming a self-aligned shallow trench isolation May 23, 2001 Abandoned
Array ( [id] => 6447487 [patent_doc_number] => 20020177303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method for sealing via sidewalls in porous low-k dielectric layers' [patent_app_type] => new [patent_app_number] => 09/863687 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2882 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177303.pdf [firstpage_image] =>[orig_patent_app_number] => 09863687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863687
Method for sealing via sidewalls in porous low-k dielectric layers May 22, 2001 Abandoned
Array ( [id] => 7162060 [patent_doc_number] => 20050085069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Dual damascene partial gap fill polymer fabrication process' [patent_app_type] => utility [patent_app_number] => 09/863647 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2544 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20050085069.pdf [firstpage_image] =>[orig_patent_app_number] => 09863647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863647
Dual damascene partial gap fill polymer fabrication process May 22, 2001 Issued
Array ( [id] => 1324361 [patent_doc_number] => 06602782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Methods for forming metal wiring layers and metal interconnects and metal interconnects formed thereby' [patent_app_type] => B2 [patent_app_number] => 09/862937 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3575 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602782.pdf [firstpage_image] =>[orig_patent_app_number] => 09862937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862937
Methods for forming metal wiring layers and metal interconnects and metal interconnects formed thereby May 21, 2001 Issued
Array ( [id] => 6095890 [patent_doc_number] => 20020052084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Buried channel strained silicon FET using a supply layer created through ion implantation' [patent_app_type] => new [patent_app_number] => 09/859137 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4288 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052084.pdf [firstpage_image] =>[orig_patent_app_number] => 09859137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/859137
Buried channel strained silicon FET using a supply layer created through ion implantation May 15, 2001 Issued
Array ( [id] => 6669000 [patent_doc_number] => 20030113984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor wafer thinning method, and thin semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/276537 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3673 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113984.pdf [firstpage_image] =>[orig_patent_app_number] => 10276537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/276537
Semiconductor wafer thinning method, and thin semiconductor wafer May 10, 2001 Issued
Array ( [id] => 1354818 [patent_doc_number] => 06576545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers' [patent_app_type] => B1 [patent_app_number] => 09/819987 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576545.pdf [firstpage_image] =>[orig_patent_app_number] => 09819987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819987
Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers Mar 28, 2001 Issued
Array ( [id] => 1209188 [patent_doc_number] => 06713318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Flip chip interconnection using no-clean flux' [patent_app_type] => B2 [patent_app_number] => 09/820547 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4027 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713318.pdf [firstpage_image] =>[orig_patent_app_number] => 09820547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820547
Flip chip interconnection using no-clean flux Mar 27, 2001 Issued
Array ( [id] => 1291100 [patent_doc_number] => 06630387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method for forming capacitor of semiconductor memory device using electroplating method' [patent_app_type] => B2 [patent_app_number] => 09/812407 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4895 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630387.pdf [firstpage_image] =>[orig_patent_app_number] => 09812407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812407
Method for forming capacitor of semiconductor memory device using electroplating method Mar 18, 2001 Issued
Array ( [id] => 6897460 [patent_doc_number] => 20010045625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof' [patent_app_type] => new [patent_app_number] => 09/809917 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9061 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045625.pdf [firstpage_image] =>[orig_patent_app_number] => 09809917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809917
Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof Mar 15, 2001 Issued
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