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Charles Chiang Chow

Examiner (ID: 5644)

Most Active Art Unit
2618
Art Unit(s)
2685, 2649, 2741, 2618, 2749, 2684
Total Applications
615
Issued Applications
432
Pending Applications
47
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1409615 [patent_doc_number] => 06528390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Process for fabricating a non-volatile memory device' [patent_app_type] => B2 [patent_app_number] => 09/798667 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2201 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528390.pdf [firstpage_image] =>[orig_patent_app_number] => 09798667 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798667
Process for fabricating a non-volatile memory device Mar 1, 2001 Issued
Array ( [id] => 6884939 [patent_doc_number] => 20010039101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Method for converting a reclaim wafer into a semiconductor wafer' [patent_app_type] => new [patent_app_number] => 09/791327 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039101.pdf [firstpage_image] =>[orig_patent_app_number] => 09791327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791327
Method for converting a reclaim wafer into a semiconductor wafer Feb 22, 2001 Abandoned
Array ( [id] => 1196816 [patent_doc_number] => 06727195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method and system for decreasing the spaces between wordlines' [patent_app_type] => B2 [patent_app_number] => 09/777457 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5628 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727195.pdf [firstpage_image] =>[orig_patent_app_number] => 09777457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777457
Method and system for decreasing the spaces between wordlines Feb 5, 2001 Issued
09/744877 Process for forming an oxide layer of non-uniform thickness of a silicon substrate Jan 28, 2001 Abandoned
Array ( [id] => 6888517 [patent_doc_number] => 20010023972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Method for eliminating development related defects in photoresist masks' [patent_app_type] => new [patent_app_number] => 09/756997 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4360 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023972.pdf [firstpage_image] =>[orig_patent_app_number] => 09756997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756997
Method for eliminating development related defects in photoresist masks Jan 7, 2001 Issued
Array ( [id] => 6631068 [patent_doc_number] => 20020086529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Actively cooled dispenser system for improved resistivity and phase control in metal CVD from organometallic precursors' [patent_app_type] => new [patent_app_number] => 09/753977 [patent_app_country] => US [patent_app_date] => 2001-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4135 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086529.pdf [firstpage_image] =>[orig_patent_app_number] => 09753977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753977
Actively cooled dispenser system for improved resistivity and phase control in metal CVD from organometallic precursors Jan 2, 2001 Abandoned
Array ( [id] => 5922077 [patent_doc_number] => 20020115285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Mechanically reinforced highly porous low dielectric constant films' [patent_app_type] => new [patent_app_number] => 09/745397 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4942 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20020115285.pdf [firstpage_image] =>[orig_patent_app_number] => 09745397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745397
Mechanically reinforced highly porous low dielectric constant films Dec 20, 2000 Issued
Array ( [id] => 1324354 [patent_doc_number] => 06602781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Metal silicide gate transistors' [patent_app_type] => B1 [patent_app_number] => 09/734207 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3504 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602781.pdf [firstpage_image] =>[orig_patent_app_number] => 09734207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734207
Metal silicide gate transistors Dec 11, 2000 Issued
Array ( [id] => 6875536 [patent_doc_number] => 20010000629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Semiconductor device and process of producing the same' [patent_app_type] => new-utility [patent_app_number] => 09/731195 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4957 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000629.pdf [firstpage_image] =>[orig_patent_app_number] => 09731195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731195
Semiconductor device and process of producing the same Dec 5, 2000 Abandoned
Array ( [id] => 6209356 [patent_doc_number] => 20020072210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method for forming liner layer in sin spacer' [patent_app_type] => new [patent_app_number] => 09/725067 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2642 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072210.pdf [firstpage_image] =>[orig_patent_app_number] => 09725067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725067
Method for forming liner layer in sin spacer Nov 28, 2000 Abandoned
Array ( [id] => 1245742 [patent_doc_number] => 06677231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method for increasing adhesion ability of dielectric material in semiconductor' [patent_app_type] => B1 [patent_app_number] => 09/715657 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677231.pdf [firstpage_image] =>[orig_patent_app_number] => 09715657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715657
Method for increasing adhesion ability of dielectric material in semiconductor Nov 16, 2000 Issued
Array ( [id] => 1273738 [patent_doc_number] => 06649454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method for fabricating a charge coupled device' [patent_app_type] => B1 [patent_app_number] => 09/709927 [patent_app_country] => US [patent_app_date] => 2000-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649454.pdf [firstpage_image] =>[orig_patent_app_number] => 09709927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709927
Method for fabricating a charge coupled device Nov 9, 2000 Issued
Array ( [id] => 1362056 [patent_doc_number] => 06569766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method for forming a silicide of metal with a high melting point in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/697508 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4437 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569766.pdf [firstpage_image] =>[orig_patent_app_number] => 09697508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697508
Method for forming a silicide of metal with a high melting point in a semiconductor device Oct 26, 2000 Issued
Array ( [id] => 1034478 [patent_doc_number] => 06875687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Capping layer for extreme low dielectric constant films' [patent_app_type] => utility [patent_app_number] => 09/692527 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8199 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/875/06875687.pdf [firstpage_image] =>[orig_patent_app_number] => 09692527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/692527
Capping layer for extreme low dielectric constant films Oct 17, 2000 Issued
Array ( [id] => 7645686 [patent_doc_number] => 06472283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'MOS transistor processing utilizing UV-nitride removable spacer and HF etch' [patent_app_type] => B1 [patent_app_number] => 09/667787 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 5620 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472283.pdf [firstpage_image] =>[orig_patent_app_number] => 09667787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667787
MOS transistor processing utilizing UV-nitride removable spacer and HF etch Sep 21, 2000 Issued
Array ( [id] => 650968 [patent_doc_number] => 07112545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-26 [patent_title] => 'Passivation of material using ultra-fast pulsed laser' [patent_app_type] => utility [patent_app_number] => 10/069768 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5233 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112545.pdf [firstpage_image] =>[orig_patent_app_number] => 10069768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/069768
Passivation of material using ultra-fast pulsed laser Sep 10, 2000 Issued
Array ( [id] => 1315589 [patent_doc_number] => 06607981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Method for forming a Cu interconnect pattern' [patent_app_type] => B1 [patent_app_number] => 09/656657 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 4529 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607981.pdf [firstpage_image] =>[orig_patent_app_number] => 09656657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656657
Method for forming a Cu interconnect pattern Sep 6, 2000 Issued
Array ( [id] => 1315361 [patent_doc_number] => 06607943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Low profile ball grid array package' [patent_app_type] => B1 [patent_app_number] => 09/632087 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3583 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607943.pdf [firstpage_image] =>[orig_patent_app_number] => 09632087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632087
Low profile ball grid array package Aug 1, 2000 Issued
Array ( [id] => 1419410 [patent_doc_number] => 06506675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Copper film selective formation method' [patent_app_type] => B1 [patent_app_number] => 09/612237 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 8440 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506675.pdf [firstpage_image] =>[orig_patent_app_number] => 09612237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612237
Copper film selective formation method Jul 6, 2000 Issued
Array ( [id] => 1414513 [patent_doc_number] => 06521513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Silicon wafer configuration and method for forming same' [patent_app_type] => B1 [patent_app_number] => 09/609617 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3773 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521513.pdf [firstpage_image] =>[orig_patent_app_number] => 09609617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609617
Silicon wafer configuration and method for forming same Jul 4, 2000 Issued
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