Charles Chiang Chow

Array ( [id] => 1414336 [patent_doc_number] => 06521501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method of forming a CMOS transistor having ultra shallow source and drain regions' [patent_app_type] => B1 [patent_app_number] => 09/310170 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1919 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521501.pdf [firstpage_image] =>[orig_patent_app_number] => 09310170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602594 [patent_doc_number] => 06432773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Memory cell having an ONO film with an ONO sidewall and method of fabricating same' [patent_app_type] => B1 [patent_app_number] => 09/288597 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 4344 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432773.pdf [firstpage_image] =>[orig_patent_app_number] => 09288597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1485227 [patent_doc_number] => 06365465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques' [patent_app_type] => B1 [patent_app_number] => 09/272297 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 51 [patent_no_of_words] => 5446 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365465.pdf [firstpage_image] =>[orig_patent_app_number] => 09272297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309683 [patent_doc_number] => 06316280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method of manufacturing semiconductor devices separated from a wafer' [patent_app_type] => 1 [patent_app_number] => 9/271257 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 50 [patent_no_of_words] => 4350 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316280.pdf [firstpage_image] =>[orig_patent_app_number] => 271257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4328992 [patent_doc_number] => 06312995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'MOS transistor with assisted-gates and ultra-shallow \"Psuedo\" source and drain extensions for ultra-large-scale integration' [patent_app_type] => 1 [patent_app_number] => 9/263557 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2978 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312995.pdf [firstpage_image] =>[orig_patent_app_number] => 263557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1101569 [patent_doc_number] => 06815251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'High density modularity for IC\'s' [patent_app_type] => B1 [patent_app_number] => 09/241177 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3503 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815251.pdf [firstpage_image] =>[orig_patent_app_number] => 09241177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258103 [patent_doc_number] => 06258615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of varying a characteristic of an optical vertical cavity structure formed by metalorganic vapor phase epitaxy' [patent_app_type] => 1 [patent_app_number] => 9/191070 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3298 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258615.pdf [firstpage_image] =>[orig_patent_app_number] => 191070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1469871 [patent_doc_number] => 06406988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method of forming fine pitch interconnections employing magnetic masks' [patent_app_type] => B1 [patent_app_number] => 09/190837 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 8175 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406988.pdf [firstpage_image] =>[orig_patent_app_number] => 09190837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1520703 [patent_doc_number] => 06413839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor device separation using a patterned laser projection' [patent_app_type] => B1 [patent_app_number] => 09/178287 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3474 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413839.pdf [firstpage_image] =>[orig_patent_app_number] => 09178287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1559943 [patent_doc_number] => 06436846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Combined preanneal/oxidation step using rapid thermal processing' [patent_app_type] => B1 [patent_app_number] => 09/146870 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2010 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436846.pdf [firstpage_image] =>[orig_patent_app_number] => 09146870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6879064 [patent_doc_number] => 20010030349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'METHOD OF GATE DOPING BY ION IMPLANTATION' [patent_app_type] => new [patent_app_number] => 09/144527 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20010030349.pdf [firstpage_image] =>[orig_patent_app_number] => 09144527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381192 [patent_doc_number] => 06261908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Buried local interconnect' [patent_app_type] => 1 [patent_app_number] => 9/123177 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261908.pdf [firstpage_image] =>[orig_patent_app_number] => 123177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1435919 [patent_doc_number] => 06355562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Adhesion promotion method for CVD copper metallization in IC applications' [patent_app_type] => B1 [patent_app_number] => 09/108260 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6417 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355562.pdf [firstpage_image] =>[orig_patent_app_number] => 09108260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1528099 [patent_doc_number] => 06479368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Method of manufacturing a semiconductor device having a shallow trench isolating region' [patent_app_type] => B1 [patent_app_number] => 09/033067 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2336 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479368.pdf [firstpage_image] =>[orig_patent_app_number] => 09033067 [rel_patent_id] =>[rel_patent_doc_number] =>)