Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16731448 [patent_doc_number] => 20210098596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => THIN FILM STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/036469 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036469
THIN FILM STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME Sep 28, 2020 Abandoned
Array ( [id] => 18137236 [patent_doc_number] => 11562925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Method of depositing multilayer stack including copper over features of a device structure [patent_app_type] => utility [patent_app_number] => 17/036038 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 10208 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036038
Method of depositing multilayer stack including copper over features of a device structure Sep 28, 2020 Issued
Array ( [id] => 17870697 [patent_doc_number] => 20220293434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/636650 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636650 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636650
Semiconductor manufacturing apparatus and method of manufacturing semiconductor device using the same, and semiconductor device Sep 28, 2020 Issued
Array ( [id] => 18205392 [patent_doc_number] => 11587795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Planarization apparatus including superstrate chuck with bendable periphery [patent_app_type] => utility [patent_app_number] => 17/035212 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5674 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035212
Planarization apparatus including superstrate chuck with bendable periphery Sep 27, 2020 Issued
Array ( [id] => 17971272 [patent_doc_number] => 11488820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Method of fabricating layered structure [patent_app_type] => utility [patent_app_number] => 17/035197 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4646 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035197
Method of fabricating layered structure Sep 27, 2020 Issued
Array ( [id] => 19213606 [patent_doc_number] => 12002678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Gate spacing in integrated circuit structures [patent_app_type] => utility [patent_app_number] => 17/033228 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 156 [patent_no_of_words] => 15083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033228 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033228
Gate spacing in integrated circuit structures Sep 24, 2020 Issued
Array ( [id] => 17485907 [patent_doc_number] => 20220093411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR FABRICATING HIGH-VOLTAGE (HV) TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/030158 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030158
Method for fabricating high-voltage (HV) transistor Sep 22, 2020 Issued
Array ( [id] => 18000928 [patent_doc_number] => 11502039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor package and method [patent_app_type] => utility [patent_app_number] => 17/026898 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026898
Semiconductor package and method Sep 20, 2020 Issued
Array ( [id] => 16545037 [patent_doc_number] => 20200411452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/018381 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018381
Method of fabricating semiconductor device including dummy via anchored to dummy metal layer Sep 10, 2020 Issued
Array ( [id] => 17745640 [patent_doc_number] => 11393721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 17/015360 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8533 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015360
Wafer processing method Sep 8, 2020 Issued
Array ( [id] => 18693929 [patent_doc_number] => 20230324331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SENSOR [patent_app_type] => utility [patent_app_number] => 18/041514 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18041514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/041514
SENSOR Sep 7, 2020 Abandoned
Array ( [id] => 16516102 [patent_doc_number] => 20200395360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/007127 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007127
Integrated circuit and manufacturing method thereof Aug 30, 2020 Issued
Array ( [id] => 18872326 [patent_doc_number] => 11860120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Integrated circuit with biofets and fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/007973 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007973
Integrated circuit with biofets and fabrication thereof Aug 30, 2020 Issued
Array ( [id] => 16509365 [patent_doc_number] => 20200388621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => REDUCING GATE INDUCED DRAIN LEAKAGE IN DRAM WORDLINE [patent_app_type] => utility [patent_app_number] => 17/002415 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002415
Reducing gate induced drain leakage in DRAM wordline Aug 24, 2020 Issued
Array ( [id] => 16995389 [patent_doc_number] => 20210233809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => LOW-K DIELECTRIC DAMAGE PREVENTION [patent_app_type] => utility [patent_app_number] => 16/991665 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991665
Low-k dielectric damage prevention Aug 11, 2020 Issued
Array ( [id] => 19185288 [patent_doc_number] => 11991906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Display substrate and manufacturing method thereof, display device [patent_app_type] => utility [patent_app_number] => 17/276282 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17276282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/276282
Display substrate and manufacturing method thereof, display device Jul 30, 2020 Issued
Array ( [id] => 16456030 [patent_doc_number] => 20200365456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => LOW RESISTIVITY FILMS CONTAINING MOLYBDENUM [patent_app_type] => utility [patent_app_number] => 16/947286 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947286
LOW RESISTIVITY FILMS CONTAINING MOLYBDENUM Jul 26, 2020 Abandoned
Array ( [id] => 16440552 [patent_doc_number] => 20200357879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => Power and Data Routing Structures for Organic Light-Emitting Diode Displays [patent_app_type] => utility [patent_app_number] => 16/939995 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939995
Power and data routing structures for organic light-emitting diode displays Jul 26, 2020 Issued
Array ( [id] => 17158957 [patent_doc_number] => 20210320008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/938646 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/938646
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Jul 23, 2020 Abandoned
Array ( [id] => 17833621 [patent_doc_number] => 20220270925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => FLEXING SEMICONDUCTOR STRUCTURES AND RELATED TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/628374 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17628374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/628374
FLEXING SEMICONDUCTOR STRUCTURES AND RELATED TECHNIQUES Jul 21, 2020 Pending
Menu