Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15488507 [patent_doc_number] => 10559615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Methods for high-dynamic-range color imaging [patent_app_type] => utility [patent_app_number] => 15/943651 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 11937 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943651
Methods for high-dynamic-range color imaging Apr 1, 2018 Issued
Array ( [id] => 15458163 [patent_doc_number] => 20200041906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => COMPOSITION FOR FORMING SILICON-CONTAINING RESIST UNDERLAYER FILM HAVING CARBONYL STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/499533 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16499533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/499533
COMPOSITION FOR FORMING SILICON-CONTAINING RESIST UNDERLAYER FILM HAVING CARBONYL STRUCTURE Mar 29, 2018 Abandoned
Array ( [id] => 16609260 [patent_doc_number] => 10910274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Backside processed semiconductor device [patent_app_type] => utility [patent_app_number] => 15/922541 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4271 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922541
Backside processed semiconductor device Mar 14, 2018 Issued
Array ( [id] => 14382233 [patent_doc_number] => 20190165029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => IMAGE SENSOR WITH PAD STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/907654 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907654
Image sensor with pad structure Feb 27, 2018 Issued
Array ( [id] => 14050255 [patent_doc_number] => 20190081235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/907907 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907907
SEMICONDUCTOR MEMORY DEVICE Feb 27, 2018 Abandoned
Array ( [id] => 13435159 [patent_doc_number] => 20180269122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => PRINTED SUBSTRATE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/907883 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907883
PRINTED SUBSTRATE AND ELECTRONIC DEVICE Feb 27, 2018 Abandoned
Array ( [id] => 14317127 [patent_doc_number] => 20190148267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => Semiconductor Package and Method [patent_app_type] => utility [patent_app_number] => 15/907474 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907474 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907474
Semiconductor package and method Feb 27, 2018 Issued
Array ( [id] => 13392675 [patent_doc_number] => 20180247880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => Chip Packaging System [patent_app_type] => utility [patent_app_number] => 15/907598 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907598 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907598
Chip Packaging System Feb 27, 2018 Abandoned
Array ( [id] => 16324231 [patent_doc_number] => 10784203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Semiconductor package and method [patent_app_type] => utility [patent_app_number] => 15/907869 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907869 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907869
Semiconductor package and method Feb 27, 2018 Issued
Array ( [id] => 13878867 [patent_doc_number] => 20190035774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => LTHC as Charging Barrier in InFO Package Formation [patent_app_type] => utility [patent_app_number] => 15/907409 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907409
LTHC as charging barrier in InFO package formation Feb 27, 2018 Issued
Array ( [id] => 15315877 [patent_doc_number] => 10522656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Forming epitaxial structures in fin field effect transistors [patent_app_type] => utility [patent_app_number] => 15/907427 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 8900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907427
Forming epitaxial structures in fin field effect transistors Feb 27, 2018 Issued
Array ( [id] => 17787782 [patent_doc_number] => 11410918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier [patent_app_type] => utility [patent_app_number] => 15/907717 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907717
Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier Feb 27, 2018 Issued
Array ( [id] => 14043613 [patent_doc_number] => 20190077913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => Dielectric Film Forming Composition [patent_app_type] => utility [patent_app_number] => 15/907332 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907332
Dielectric film forming composition Feb 27, 2018 Issued
Array ( [id] => 15580619 [patent_doc_number] => 10580702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/907573 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 70 [patent_no_of_words] => 9467 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907573
Semiconductor device Feb 27, 2018 Issued
Array ( [id] => 14828079 [patent_doc_number] => 10411055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Sensor package structure [patent_app_type] => utility [patent_app_number] => 15/907360 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4871 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907360
Sensor package structure Feb 27, 2018 Issued
Array ( [id] => 14475887 [patent_doc_number] => 20190189591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR STORAGE CUBE WITH ENHANCED SIDEWALL PLANARITY [patent_app_type] => utility [patent_app_number] => 15/907491 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907491
SEMICONDUCTOR STORAGE CUBE WITH ENHANCED SIDEWALL PLANARITY Feb 27, 2018 Abandoned
Array ( [id] => 15857383 [patent_doc_number] => 10643990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Ultra-high voltage resistor [patent_app_type] => utility [patent_app_number] => 15/907866 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907866 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907866
Ultra-high voltage resistor Feb 27, 2018 Issued
Array ( [id] => 14784889 [patent_doc_number] => 20190267342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost Package [patent_app_type] => utility [patent_app_number] => 15/907446 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907446 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907446
Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost Package Feb 27, 2018 Abandoned
Array ( [id] => 15286463 [patent_doc_number] => 10515901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => InFO-POP structures with TIVs having cavities [patent_app_type] => utility [patent_app_number] => 15/907473 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 37 [patent_no_of_words] => 8273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907473
InFO-POP structures with TIVs having cavities Feb 27, 2018 Issued
Array ( [id] => 14785283 [patent_doc_number] => 20190267539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => HALL EFFECT SENSORS WITH A METAL LAYER COMPRISING AN INTERCONNECT AND A TRACE [patent_app_type] => utility [patent_app_number] => 15/907000 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907000
Hall effect sensors with a metal layer comprising an interconnect and a trace Feb 26, 2018 Issued
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